Firmware: Add drtio_eem.rs support

- Port from Artiq repo - Initialize the drtio_eem on main, rtio_clocking - Driver for eem_transceiver
kasli_soc: Add support for shuttler on gateware
2023-10-09 17:40:44 +08:00 · 2023-10-09 17:40:44 +08:00 · 2023-10-09 17:40:35 +08:00
14 changed files with 147 additions and 105 deletions
--- a/.gitignore
+++ b/.gitignore
@ -3,11 +3,3 @@ examples/*.elf
 __pycache__

 build
-
-src/libboard_artiq/Cargo.toml
-src/libc/Cargo.toml
-src/libdyld/Cargo.toml
-src/libio/Cargo.toml
-src/libksupport/Cargo.toml
-src/runtime/Cargo.toml
-src/satman/Cargo.toml
--- a/README.md
+++ b/README.md
@ -58,6 +58,7 @@ Notes:
 - When calling make, you need to specify both the variant and firmware type.
 - Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
 - If the board is connected to the local machine, use the ``local_run.sh`` script.
+- To update ``zynq-rs``, update the cargo files as per usual for Rust projects, but also keep ``flake.lock`` in sync.

 License
 -------
--- a/flake.nix
+++ b/flake.nix
@ -122,6 +122,9 @@
        src = ./src;
        cargoLock = { 
          lockFile = src/Cargo.lock;
+          outputHashes = {
+            "libasync-0.0.0" = "sha256-MppR7yxs3cjG7tQc82vX0MhyN71CJL2QWkM65F5hrFU=";
+          };
        };

        nativeBuildInputs = [
@ -135,7 +138,6 @@
          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
-          export ZYNQ_RS=${zynq-rs}
          make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
        '';

@ -249,19 +251,18 @@
        '';
    };

-    fmt-check = pkgs.stdenvNoCC.mkDerivation {
+    fmt-check = pkgs.stdenv.mkDerivation {
      name = "fmt-check";

-      src = ./src;
+      nativeBuildInputs = [
+        rust
+      ];

-      nativeBuildInputs = [ rust pkgs.gnumake ];
-
-      phases = [ "unpackPhase" "buildPhase" ];
+      phases = [ "buildPhase" ];

      buildPhase =
        ''
-        export ZYNQ_RS=${zynq-rs}
-        make manifests
+        cd ${self}/src
        cargo fmt -- --check
        touch $out
        '';
@ -380,7 +381,6 @@
      ];
      XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include";
-      ZYNQ_RS = "${zynq-rs}";
      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
      SZL = "${zynqpkgs.szl}";
    };
--- a/src/Cargo.lock
+++ b/src/Cargo.lock
@ -242,13 +242,13 @@ dependencies = [
 "log_buffer",
 "nb 0.1.3",
 "unwind",
- "vcell",
 "void",
 ]

 [[package]]
 name = "libasync"
 version = "0.0.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "embedded-hal",
 "libcortex_a9",
@ -281,6 +281,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "bit_field",
 "embedded-hal",
@ -305,6 +306,7 @@ dependencies = [
 [[package]]
 name = "libconfig"
 version = "0.1.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "core_io",
 "fatfs",
@ -315,6 +317,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "bit_field",
 "libregister",
@ -330,6 +333,7 @@ checksum = "348108ab3fba42ec82ff6e9564fc4ca0247bdccdc68dd8af9764bbc79c3c8ffb"
 [[package]]
 name = "libregister"
 version = "0.0.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "bit_field",
 "vcell",
@ -339,6 +343,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
 "cc",
 "compiler_builtins",
--- a/src/Makefile
+++ b/src/Makefile
@ -7,20 +7,13 @@ runtime: ../build/runtime.bin

 satman: ../build/satman.bin

-.PHONY: all manifests
-
-manifests = libboard_artiq/Cargo.toml libc/Cargo.toml libdyld/Cargo.toml libio/Cargo.toml libksupport/Cargo.toml runtime/Cargo.toml satman/Cargo.toml
-
-$(manifests): %.toml: %.toml.tpl
-	sed s+@@ZYNQ_RS@@+$(ZYNQ_RS)+g $< > $@
-
-manifests: $(manifests)
+.PHONY: all runtime_target satman_target

 ../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/* 
 	mkdir -p ../build
 	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)

-../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
 	cd runtime && \
 	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
 	cargo xbuild --release \
@ -30,7 +23,7 @@ manifests: $(manifests)
 ../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
 	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin

-../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
 	cd satman && \
 	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
 	cargo xbuild --release \
@ -38,4 +31,4 @@ manifests: $(manifests)
 		--no-default-features --features=target_$(TARGET)

 ../build/satman.bin: ../build/firmware/armv7-none-eabihf/release/satman
-	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin
+	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -234,7 +234,8 @@ class GenericMaster(SoCCore):
            self.platform,
            self.ps7,
            txout_buf,
-            clk_sw=gtx0.tx_init.done)
+            clk_sw=gtx0.tx_init.done,
+            enable_sys5x=has_drtio_over_eem)
        self.csr_devices.append("sys_crg")
        self.crg = self.ps7 # HACK for eem_7series to find the clock
        self.crg.cd_sys = self.sys_crg.cd_sys
--- a/src/gateware/zynq_clocking.py
+++ b/src/gateware/zynq_clocking.py
@ -65,12 +65,13 @@ class ClockSwitchFSM(Module):


 class SYSCRG(Module, AutoCSR):
-    def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6):
+    def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, enable_sys5x=False):
        # assumes bootstrap clock is same freq as main and sys output
        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200 = ClockDomain()
+        if enable_sys5x:
+            self.clock_domains.cd_clk200 = ClockDomain()
+            self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)

        self.current_clock = CSRStatus()

@ -88,55 +89,105 @@ class SYSCRG(Module, AutoCSR):
        else:
            self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)

-        mmcm_locked = Signal()
-        mmcm_sys = Signal()
-        mmcm_sys4x = Signal()
-        mmcm_sys5x = Signal()
-        mmcm_clk208 = Signal()
-        mmcm_fb_clk = Signal()
-        self.specials += [
-            Instance("MMCME2_ADV",
-                p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked,
-                p_BANDWIDTH="HIGH",
-                p_REF_JITTER1=0.001,
-                p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
-                p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
-                i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
+        if enable_sys5x:
+            pll_clk200 = Signal()
+            pll_fb_clk = Signal()
+            pll_locked = Signal()
+            self.specials += [
+                Instance("PLLE2_BASE",
+                    p_CLKIN1_PERIOD=8.0,
+                    i_CLKIN1=bootstrap_clk,

-                # VCO @ 1.25GHz
-                p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
-                i_CLKFBIN=mmcm_fb_clk,
-                i_RST=self.clk_sw_fsm.o_reset,
+                    i_CLKFBIN=pll_fb_clk,
+                    o_CLKFBOUT=pll_fb_clk,
+                    o_LOCKED=pll_locked,

-                o_CLKFBOUT=mmcm_fb_clk,
+                    # VCO @ 1GHz
+                    p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,

-                p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
+                    # 200MHz for IDELAYCTRL
+                    p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
+                ),
+                Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
+                AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
+            ]

-                # 125MHz
-                p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
+            reset_counter = Signal(4, reset=15)
+            ic_reset = Signal(reset=1)
+            self.sync.clk200 += \
+                If(reset_counter != 0,
+                    reset_counter.eq(reset_counter - 1)
+                ).Else(
+                    ic_reset.eq(0)
+                )
+            self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)

-                # 625MHz
-                p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
+            mmcm_locked = Signal()
+            mmcm_sys = Signal()
+            mmcm_sys4x = Signal()
+            mmcm_sys5x = Signal()
+            mmcm_fb_clk = Signal()
+            self.specials += [
+                Instance("MMCME2_ADV",
+                    p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked,
+                    p_BANDWIDTH="HIGH",
+                    p_REF_JITTER1=0.001,
+                    p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
+                    p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
+                    i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,

-                # 208MHz
-                p_CLKOUT3_DIVIDE=6, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=mmcm_clk208,
-            ),
-            Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
-            Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
-            Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
-            Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
-            AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked),
-            AsyncResetSynchronizer(self.cd_clk200, ~mmcm_locked),
-        ]
+                    # VCO @ 1.25GHz with MULT=10
+                    p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
+                    i_CLKFBIN=mmcm_fb_clk,
+                    i_RST=self.clk_sw_fsm.o_reset,

-        reset_counter = Signal(4, reset=15)
-        ic_reset = Signal(reset=1)
-        self.sync.clk200 += \
-            If(reset_counter != 0,
-                reset_counter.eq(reset_counter - 1)
-            ).Else(
-                ic_reset.eq(0)
-            )
-        self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+                    o_CLKFBOUT=mmcm_fb_clk,
+
+                    # 500MHz. Must be more than 400MHz as per DDR3 specs.
+                    p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
+
+                    # 125MHz
+                    p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
+
+                    # 625MHz
+                    p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
+                ),
+                Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
+                Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
+                Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
+                AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked),
+            ]
+        else:
+            pll_locked = Signal()
+            pll_sys = Signal()
+            pll_sys4x = Signal()
+            fb_clk = Signal()
+            self.specials += [
+                Instance("PLLE2_ADV",
+                    p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
+                    p_BANDWIDTH="HIGH",
+                    p_REF_JITTER1=0.001,
+                    p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
+                    p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
+                    i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
+
+                    # VCO @ 1.5GHz when using 125MHz input
+                    # 1.2GHz for 100MHz (zc706)
+                    p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
+                    i_CLKFBIN=fb_clk,
+                    i_RST=self.clk_sw_fsm.o_reset,
+
+                    o_CLKFBOUT=fb_clk,
+
+                    p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
+                    o_CLKOUT0=pll_sys4x,
+
+                    p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
+                    o_CLKOUT1=pll_sys),
+
+                Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
+                Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
+                AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
+            ]

        self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
--- a/src/libboard_artiq/Cargo.toml.tpl
+++ b/src/libboard_artiq/Cargo.toml.tpl
@ -24,9 +24,9 @@ nb = "1.0"
 void = { version = "1", default-features = false }

 io = { path = "../libio", features = ["byteorder"] }
-libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }
-libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
-libregister = { path = "@@ZYNQ_RS@@/libregister" }
-libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn"] }
-libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
-libasync = { path = "@@ZYNQ_RS@@/libasync" }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["fat_lfn"] }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
--- a/src/libc/Cargo.toml.tpl
+++ b/src/libc/Cargo.toml.tpl
@ -6,7 +6,7 @@ edition = "2018"
 build = "build.rs"

 [dependencies]
-libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }

 [build-dependencies]
 cc = { version = "1.0.1" }
--- a/src/libdyld/Cargo.toml.tpl
+++ b/src/libdyld/Cargo.toml.tpl
@ -8,4 +8,4 @@ name = "dyld"

 [dependencies]
 log = "0.4"
-libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
--- a/src/libio/Cargo.toml.tpl
+++ b/src/libio/Cargo.toml.tpl
@ -11,7 +11,7 @@ path = "lib.rs"
 core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.0", default-features = false, optional = true }

-libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }

 [features]
 alloc = []
--- a/src/libksupport/Cargo.toml.tpl
+++ b/src/libksupport/Cargo.toml.tpl
@ -17,18 +17,17 @@ byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 log_buffer = { version = "1.2" }
 libm = { version = "0.2", features = ["unstable"] }
-vcell = "0.1"

-libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq", features = ["ipv6"]}
-libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
-libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
-libasync = { path = "@@ZYNQ_RS@@/libasync" }
-libregister = { path = "@@ZYNQ_RS@@/libregister" }
-libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn", "ipv6"] }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["fat_lfn", "ipv6"] }

 dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
 unwind = { path = "../libunwind" }
 libc = { path = "../libc" }
 io = { path = "../libio" }
-libboard_artiq = { path = "../libboard_artiq" }
+libboard_artiq = { path = "../libboard_artiq" }
--- a/src/runtime/Cargo.toml.tpl
+++ b/src/runtime/Cargo.toml.tpl
@ -27,12 +27,12 @@ async-recursion = "0.3"
 log_buffer = { version = "1.2" }
 vcell = "0.1"

-libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq", features = ["ipv6"]}
-libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
-libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
-libasync = { path = "@@ZYNQ_RS@@/libasync" }
-libregister = { path = "@@ZYNQ_RS@@/libregister" }
-libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn", "ipv6"] }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["fat_lfn", "ipv6"] }

 dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
--- a/src/satman/Cargo.toml.tpl
+++ b/src/satman/Cargo.toml.tpl
@ -18,12 +18,12 @@ core_io = { version = "0.1", features = ["collections"] }
 cslice = "0.3"
 embedded-hal = "0.2"

-libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq", features = ["ipv6"]}
-libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
-libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
-libasync = { path = "@@ZYNQ_RS@@/libasync" }
-libregister = { path = "@@ZYNQ_RS@@/libregister" }
-libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn", "ipv6"] }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["fat_lfn", "ipv6"] }

 libboard_artiq = { path = "../libboard_artiq" }
 unwind = { path = "../libunwind" }