zynq_clocking: add enable_sys5x option, IDELAYCTRL
- Port from artiq repo - If enable_sys5x, - add one PLL thats generate 200MHz IDELAYCTRL ref clock - add a IDELAYCTRL instance for EEM Serdes - add sys5x for EEM Serdes
parent
8eb359ee42
commit
d4e8dd1554
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@ -65,10 +65,13 @@ class ClockSwitchFSM(Module):
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, enable_sys5x=False):
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# assumes bootstrap clock is same freq as main and sys output
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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if enable_sys5x:
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
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self.current_clock = CSRStatus()
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@ -78,11 +81,6 @@ class SYSCRG(Module, AutoCSR):
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period = 1e9/freq
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pll_locked = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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fb_clk = Signal()
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self.submodules.clk_sw_fsm = ClockSwitchFSM()
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if clk_sw is None:
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@ -91,32 +89,105 @@ class SYSCRG(Module, AutoCSR):
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else:
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
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i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
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if enable_sys5x:
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pll_clk200 = Signal()
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pll_fb_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=bootstrap_clk,
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# VCO @ 1.5GHz when using 125MHz input
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# 1.2GHz for 100MHz (zc706)
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.clk_sw_fsm.o_reset,
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i_CLKFBIN=pll_fb_clk,
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o_CLKFBOUT=pll_fb_clk,
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o_LOCKED=pll_locked,
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o_CLKFBOUT=fb_clk,
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# VCO @ 1GHz
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys4x,
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# 200MHz for IDELAYCTRL
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p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
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),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
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]
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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]
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mmcm_locked = Signal()
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mmcm_sys = Signal()
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mmcm_sys4x = Signal()
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mmcm_sys5x = Signal()
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mmcm_fb_clk = Signal()
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self.specials += [
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Instance("MMCME2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
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i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
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# VCO @ 1.25GHz with MULT=10
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p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=mmcm_fb_clk,
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i_RST=self.clk_sw_fsm.o_reset,
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o_CLKFBOUT=mmcm_fb_clk,
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# 500MHz. Must be more than 400MHz as per DDR3 specs.
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p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
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# 125MHz
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p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
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# 625MHz
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
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),
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Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked),
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]
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else:
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pll_locked = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
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i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
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# VCO @ 1.5GHz when using 125MHz input
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# 1.2GHz for 100MHz (zc706)
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.clk_sw_fsm.o_reset,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys4x,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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]
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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