Compare commits
6 Commits
005f96a924
...
8fd524d36b
Author | SHA1 | Date |
---|---|---|
morgan | 8fd524d36b | |
morgan | e5aad47cb2 | |
morgan | 07b7ea04d4 | |
morgan | a9ed4aa180 | |
morgan | 68a11bf7a3 | |
morgan | 530fb2e7b0 |
|
@ -48,19 +48,6 @@ eem_iostandard_dict = {
|
||||||
def eem_iostandard(eem):
|
def eem_iostandard(eem):
|
||||||
return IOStandard(eem_iostandard_dict[eem])
|
return IOStandard(eem_iostandard_dict[eem])
|
||||||
|
|
||||||
class ClockSynthesis(Module):
|
|
||||||
def __init__(self, platform):
|
|
||||||
self.se = Signal()
|
|
||||||
|
|
||||||
clk_synth = platform.request("cdr_clk_clean_fabric")
|
|
||||||
platform.add_period_constraint(clk_synth.p, 8.0)
|
|
||||||
|
|
||||||
self.specials += [
|
|
||||||
Instance("IBUFGDS",
|
|
||||||
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
|
|
||||||
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=self.se
|
|
||||||
),
|
|
||||||
]
|
|
||||||
|
|
||||||
class SMAClkinForward(Module):
|
class SMAClkinForward(Module):
|
||||||
def __init__(self, platform):
|
def __init__(self, platform):
|
||||||
|
@ -134,11 +121,18 @@ class GenericStandalone(SoCCore):
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
|
|
||||||
self.config["HW_REV"] = description["hw_rev"]
|
self.config["HW_REV"] = description["hw_rev"]
|
||||||
|
clk_synth = platform.request("cdr_clk_clean_fabric")
|
||||||
self.submodules.clk_synth = ClockSynthesis(self.platform)
|
clk_synth_se = Signal()
|
||||||
clk_synth_se_buf = Signal()
|
clk_synth_se_buf = Signal()
|
||||||
self.specials += Instance("BUFG", i_I=self.clk_synth.se, o_O=clk_synth_se_buf)
|
platform.add_period_constraint(clk_synth.p, 8.0)
|
||||||
|
|
||||||
|
self.specials += [
|
||||||
|
Instance("IBUFGDS",
|
||||||
|
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
|
||||||
|
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
|
||||||
|
),
|
||||||
|
Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
|
||||||
|
]
|
||||||
fix_serdes_timing_path(platform)
|
fix_serdes_timing_path(platform)
|
||||||
self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
|
self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
|
||||||
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
|
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
|
||||||
|
@ -155,7 +149,7 @@ class GenericStandalone(SoCCore):
|
||||||
self.submodules.wrpll = wrpll.WRPLL(
|
self.submodules.wrpll = wrpll.WRPLL(
|
||||||
platform=self.platform,
|
platform=self.platform,
|
||||||
cd_ref=self.wrpll_refclk.cd_ref,
|
cd_ref=self.wrpll_refclk.cd_ref,
|
||||||
main_clk_se=self.clk_synth.se)
|
main_clk_se=clk_synth_se)
|
||||||
self.csr_devices.append("wrpll_refclk")
|
self.csr_devices.append("wrpll_refclk")
|
||||||
self.csr_devices.append("wrpll")
|
self.csr_devices.append("wrpll")
|
||||||
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
|
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
|
||||||
|
@ -275,12 +269,14 @@ class GenericMaster(SoCCore):
|
||||||
self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
|
self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
|
||||||
|
|
||||||
if with_wrpll:
|
if with_wrpll:
|
||||||
self.submodules.clk_synth = ClockSynthesis(self.platform)
|
clk_synth = platform.request("cdr_clk_clean_fabric")
|
||||||
|
clk_synth_se = Signal()
|
||||||
|
self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
|
||||||
self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
|
self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
|
||||||
self.submodules.wrpll = wrpll.WRPLL(
|
self.submodules.wrpll = wrpll.WRPLL(
|
||||||
platform=self.platform,
|
platform=self.platform,
|
||||||
cd_ref=self.wrpll_refclk.cd_ref,
|
cd_ref=self.wrpll_refclk.cd_ref,
|
||||||
main_clk_se=self.clk_synth.se)
|
main_clk_se=clk_synth_se)
|
||||||
self.csr_devices.append("wrpll_refclk")
|
self.csr_devices.append("wrpll_refclk")
|
||||||
self.csr_devices.append("wrpll")
|
self.csr_devices.append("wrpll")
|
||||||
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
|
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
|
||||||
|
@ -584,11 +580,13 @@ class GenericSatellite(SoCCore):
|
||||||
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
|
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
|
||||||
|
|
||||||
if with_wrpll:
|
if with_wrpll:
|
||||||
self.submodules.clk_synth = ClockSynthesis(self.platform)
|
clk_synth = platform.request("cdr_clk_clean_fabric")
|
||||||
|
clk_synth_se = Signal()
|
||||||
|
self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
|
||||||
self.submodules.wrpll = wrpll.WRPLL(
|
self.submodules.wrpll = wrpll.WRPLL(
|
||||||
platform=self.platform,
|
platform=self.platform,
|
||||||
cd_ref=self.gt_drtio.cd_rtio_rx0,
|
cd_ref=self.gt_drtio.cd_rtio_rx0,
|
||||||
main_clk_se=self.clk_synth.se)
|
main_clk_se=clk_synth_se)
|
||||||
self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
|
self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
|
||||||
self.csr_devices.append("wrpll_skewtester")
|
self.csr_devices.append("wrpll_skewtester")
|
||||||
self.csr_devices.append("wrpll")
|
self.csr_devices.append("wrpll")
|
||||||
|
|
Loading…
Reference in New Issue