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7 Commits
8fd524d36b
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005f96a924
Author | SHA1 | Date |
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morgan | 005f96a924 | |
morgan | 682e92b17e | |
morgan | fbf973efd0 | |
morgan | a163d29ec0 | |
morgan | 9d27741de8 | |
morgan | 303aad20ac | |
morgan | 945a9f1c47 |
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@ -48,6 +48,19 @@ eem_iostandard_dict = {
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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class ClockSynthesis(Module):
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def __init__(self, platform):
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self.se = Signal()
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clk_synth = platform.request("cdr_clk_clean_fabric")
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=self.se
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),
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]
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class SMAClkinForward(Module):
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def __init__(self, platform):
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@ -121,18 +134,11 @@ class GenericStandalone(SoCCore):
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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clk_synth_se_buf = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("BUFG", i_I=self.clk_synth.se, o_O=clk_synth_se_buf)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
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),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
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]
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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@ -149,7 +155,7 @@ class GenericStandalone(SoCCore):
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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main_clk_se=self.clk_synth.se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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@ -269,14 +275,12 @@ class GenericMaster(SoCCore):
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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if with_wrpll:
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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main_clk_se=self.clk_synth.se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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@ -580,13 +584,11 @@ class GenericSatellite(SoCCore):
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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if with_wrpll:
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.gt_drtio.cd_rtio_rx0,
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main_clk_se=clk_synth_se)
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main_clk_se=self.clk_synth.se)
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self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
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self.csr_devices.append("wrpll_skewtester")
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self.csr_devices.append("wrpll")
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