Commit Graph

716 Commits

Author SHA1 Message Date
f0588c49ed rpc: make receive async 2020-06-07 20:24:41 +08:00
ef4bdbb668 rpc: enable logging 2020-06-07 20:23:43 +08:00
93349206ed add Mandelbrot example 2020-06-07 15:13:31 +08:00
4b8bbdc3dc send RPC requests to host 2020-06-07 15:13:20 +08:00
1f23a1b86c enable FPU on Core1 2020-06-07 15:12:34 +08:00
7216e9c4be update cargoSha256 2020-06-05 19:26:50 +08:00
ed21457f28 replace libio with core_io
* based on https://github.com/jethrogb/rust-core_io but could not get the packaging scripts to work
  and the repos is unmaintained anyway, so just copied the result
* more features and more up-to-date
* compatible with the fatfs crate
2020-06-05 17:14:36 +08:00
a915ed172a send RPC requests to comms CPU, handle kernel termination 2020-06-05 11:48:34 +08:00
8e68e65ca7 remove dead code 2020-06-05 11:47:36 +08:00
aff7c3a40b add local run script 2020-06-05 11:46:11 +08:00
d65df2f454 rpc: revert to libio
* Recursive async fns in Rust are a mess and not usable.
* When doing ARTIQ async RPCs, it is simpler to encode the buffer on the kernel CPU and pass that to the comms CPU,
  instead of tracking when kernel CPU memory with the RPC values can be freed.
2020-06-03 11:17:49 +08:00
9c0cf7e84c remove unneeded import 2020-06-03 11:17:37 +08:00
6454f994af add libio from ARTIQ 2020-06-03 11:17:28 +08:00
cb24b82e68 rpc: strings 2020-06-01 18:21:04 +08:00
7aa9a95c21 add RPC protocol module (WIP) 2020-06-01 18:02:21 +08:00
15b2b253cf build for NIST variants 2020-05-14 15:30:50 +08:00
af08b1ad00 update dependencies 2020-05-14 09:28:16 +08:00
1222db56e1 use different user_led to avoid VADJ problems with NIST backplanes 2020-05-14 09:23:43 +08:00
aeefdc862d update dependencies 2020-05-09 13:48:27 +08:00
7c6f57540e prevent cargo xbuild from creating sysroot in source tree. Closes #6 2020-05-09 13:21:55 +08:00
b2fe33f6ea zc706: add support for NIST backplanes 2020-05-07 17:05:00 +08:00
4464b85ab3 move build artifacts out of tree 2020-05-07 13:52:40 +08:00
743b0e198d cargo: remove outdated runner entry 2020-05-07 13:50:21 +08:00
47261a1d84 update comment/message 2020-05-07 12:43:53 +08:00
d08f4552ab libdyld: fix pltrel_sz, remove debug output 2020-05-07 01:44:26 +02:00
90faeb6fa2 use new core1 startup mechanism 2020-05-06 22:16:34 +08:00
ae2cee5f7e also work around mkbootimage potential bug with szl 2020-05-06 17:47:27 +08:00
27466036a7 work around boot.bin/fsbl problems
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
2020-05-06 17:38:01 +08:00
7c22b72129 add FSBL startup route
Not working (Zynq sucks) and not debuggable (can't get UART output from FSBL even with official binaries...)
2020-05-06 16:53:54 +08:00
1211a6d066 build FSBL 2020-05-06 16:02:44 +08:00
11d839d8a6 update cargoSha256 2020-05-04 23:02:51 +08:00
198985cd6d runtime: check PL DONE 2020-05-04 22:27:15 +08:00
07efdc6799 szl: cleanup 2020-05-04 22:17:59 +08:00
cbd591b86b update dependencies 2020-05-03 09:59:24 +08:00
9750bb8aa8 default.nix: change <artiq-fast> syntax 2020-05-03 02:25:19 +02:00
b7695d9313 typo 2020-05-02 11:50:29 +08:00
bca2b3fe50 comms: add comment about closed connection handling 2020-05-02 11:44:10 +08:00
11b58d801d default.nix: build SD card contents 2020-05-01 11:23:00 +08:00
b7c5a56470 remote_run: fixes 2020-05-01 11:22:45 +08:00
53e1af81b6 add Antmicro Zynq mkbootimage utility 2020-05-01 10:51:13 +08:00
dffbab2707 default.nix: fix szl filenames 2020-05-01 10:48:23 +08:00
a2ea0fbc9f README: fix formatting 2020-05-01 10:09:31 +08:00
90a19f9986 Merge branch 'master' of git.m-labs.hk:M-Labs/artiq-zynq 2020-05-01 10:08:17 +08:00
2439ba1f88 add impure incremental build process, document 2020-05-01 10:07:38 +08:00
b02c051007 libdyld: fix hash+symtab sizes 2020-05-01 03:20:38 +02:00
92ae487143 update zc706 dependencies 2020-05-01 02:18:52 +02:00
48025339b3 comms: handle connection termination 2020-05-01 02:09:00 +02:00
895a3f47e2 libdyld: refactor 2020-05-01 01:19:10 +02:00
c28c567e72 pure Nix build system 2020-04-30 21:04:28 +08:00
0ebe14c474 sync with zc706 repos 2020-04-30 19:33:57 +08:00