 Sebastien Bourdeauducq
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506c741238
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support absence of gateware RTIO clock selection mux
Hydra zc706-hitl-tests Hydra build #130237 of artiq:zynq:zc706-hitl-tests
Details
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2021-02-15 21:41:30 +08:00 |
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Sebastien Bourdeauducq
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1e20259c36
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fix acpki selection
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2020-08-04 13:26:45 +08:00 |
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Sebastien Bourdeauducq
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f8d4036451
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add ACP kernel initiator
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
#55
Work-in-progress, only gateware part and build system, untested.
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2020-08-04 13:15:26 +08:00 |
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Sebastien Bourdeauducq
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523524c319
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zc706: add RTIO log channels
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2020-07-19 14:05:35 +08:00 |
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Sebastien Bourdeauducq
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f69e41af5e
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gateware: fix VADJ I/O standard conflict
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2020-07-16 17:58:31 +08:00 |
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Sebastien Bourdeauducq
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6a361893c2
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gateware: make LEDs common to all variants
Makes quick testing easier.
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2020-07-16 17:36:27 +08:00 |
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Sebastien Bourdeauducq
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8e758ecc17
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add RTIO analyzer core (untested)
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2020-07-15 23:06:34 +08:00 |
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Sebastien Bourdeauducq
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a7073edf79
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add DMA core (untested)
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2020-07-13 10:37:17 +08:00 |
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Sebastien Bourdeauducq
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e3ff21b1b5
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create gateware folder
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2020-07-11 17:49:54 +08:00 |