bbc1ffec8e
szl: disable ps7_init
2020-07-06 12:31:13 +08:00
bbe6812792
add network address config code
2020-07-06 12:04:22 +08:00
2df1a647df
update cargosha256
2020-07-06 01:12:23 +08:00
3bd4643009
use fpu_enable from zc706
2020-07-06 00:18:28 +08:00
6f37128911
use clang-unwrapped
2020-07-02 21:50:19 +08:00
e6028ec091
update cargosha256
2020-07-02 21:41:35 +08:00
8807854b2b
fix cargoSha256
2020-07-02 10:31:14 +08:00
d8745074b4
update dependencies
2020-06-27 02:29:45 +02:00
a71ee143ac
update dependencies
2020-06-25 20:21:44 +08:00
f750234cb5
update dependencies
2020-06-18 18:33:32 +02:00
854a50a0ba
fsbl: clean up buildInputs
2020-06-17 16:23:41 +08:00
ec9a70ecc3
FSBL: changed to self-built FSBL ( #13 )
...
Co-authored-by: pca006132 <john.lck40@gmail.com>
2020-06-17 16:19:59 +08:00
e43511c95f
update dependencies
2020-06-16 18:08:12 +08:00
0dc0bb391d
add support for loading bitstream from bootimage.
2020-06-16 17:45:54 +08:00
f9ccf908dd
update dependencies
2020-06-15 17:14:03 +08:00
dec245e637
default.nix: also use BIF format to contain bitstream for SZL
2020-06-15 17:03:27 +08:00
dc78868109
update dependencies and add fatfs
2020-06-11 17:36:23 +08:00
de2618045a
update cargoSha256
2020-06-07 22:00:23 +08:00
7216e9c4be
update cargoSha256
2020-06-05 19:26:50 +08:00
15b2b253cf
build for NIST variants
2020-05-14 15:30:50 +08:00
af08b1ad00
update dependencies
2020-05-14 09:28:16 +08:00
aeefdc862d
update dependencies
2020-05-09 13:48:27 +08:00
4464b85ab3
move build artifacts out of tree
2020-05-07 13:52:40 +08:00
90faeb6fa2
use new core1 startup mechanism
2020-05-06 22:16:34 +08:00
ae2cee5f7e
also work around mkbootimage potential bug with szl
2020-05-06 17:47:27 +08:00
27466036a7
work around boot.bin/fsbl problems
...
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
2020-05-06 17:38:01 +08:00
7c22b72129
add FSBL startup route
...
Not working (Zynq sucks) and not debuggable (can't get UART output from FSBL even with official binaries...)
2020-05-06 16:53:54 +08:00
1211a6d066
build FSBL
2020-05-06 16:02:44 +08:00
11d839d8a6
update cargoSha256
2020-05-04 23:02:51 +08:00
cbd591b86b
update dependencies
2020-05-03 09:59:24 +08:00
9750bb8aa8
default.nix: change <artiq-fast> syntax
2020-05-03 02:25:19 +02:00
11b58d801d
default.nix: build SD card contents
2020-05-01 11:23:00 +08:00
dffbab2707
default.nix: fix szl filenames
2020-05-01 10:48:23 +08:00
2439ba1f88
add impure incremental build process, document
2020-05-01 10:07:38 +08:00
c28c567e72
pure Nix build system
2020-04-30 21:04:28 +08:00
