WRPLL firmware
satman main & si549: add WRPLL select_recovered_clock satman main & si549: add helper si549 & interrupt setup si549: add tag collector to process gtx & main tags si549: add frequency counter to set BASE_ADPLL si549: add set_adpll for main & helper PLL si549: add main & helper PLL IRQ & si549: add handler for gtx & main tags irq IRQ: add docs for IRQ id
parent
05f80b579f
commit
ec506fd0ce
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@ -284,3 +284,310 @@ pub fn main_setup(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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info!("Main Si549 started");
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Ok(())
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}
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#[cfg(has_wrpll)]
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pub mod wrpll {
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use libboard_zynq::gic;
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use libcortex_a9::mutex::Mutex;
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use super::*;
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const IRQ_ID: [u8; 2] = [61, 62];
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const TIMER_WIDTH: u32 = 24;
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const COUNTER_DIV: u32 = 2;
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const ADPLL_MAX: i32 = (950.0 / 0.0001164) as i32;
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static BASE_ADPLL: Mutex<i32> = Mutex::new(0);
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static H_INTEGRATOR: Mutex<i32> = Mutex::new(0);
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static M_INTEGRATOR: Mutex<i32> = Mutex::new(0);
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#[derive(Clone, Copy)]
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pub enum IRQ {
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GTXTag,
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MainTag,
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}
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mod tag_collector {
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use super::*;
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const BEATING_PERIOD: i32 = 0x4000;
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const BEATING_HALFPERIOD: i32 = 0x2000;
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// for helper PLL
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static LAST_GTX_TAG: Mutex<u32> = Mutex::new(0);
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static FIRST_GTX_INTERRUPT: Mutex<bool> = Mutex::new(false);
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static PERIOD_DET_READY: Mutex<bool> = Mutex::new(false);
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// for main PLL
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static GTX_TAG: Mutex<u32> = Mutex::new(0);
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static GTX_TAG_READY: Mutex<bool> = Mutex::new(false);
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static MAIN_TAG: Mutex<u32> = Mutex::new(0);
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static MAIN_TAG_READY: Mutex<bool> = Mutex::new(false);
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pub fn reset() {
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clear_period_det_ready();
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clear_phase_det_ready();
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*LAST_GTX_TAG.lock() = 0;
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*FIRST_GTX_INTERRUPT.lock() = true;
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*GTX_TAG.lock() = 0;
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*MAIN_TAG.lock() = 0;
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}
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pub fn clear_period_det_ready() {
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*PERIOD_DET_READY.lock() = false;
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}
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pub fn clear_phase_det_ready() {
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*GTX_TAG_READY.lock() = false;
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*MAIN_TAG_READY.lock() = false;
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}
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pub fn collect_tags(interrupt: IRQ) {
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match interrupt {
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IRQ::GTXTag => {
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let mut gtx_tag_lock = GTX_TAG.lock();
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if !(*FIRST_GTX_INTERRUPT.lock()) {
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*LAST_GTX_TAG.lock() = *gtx_tag_lock;
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}
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*gtx_tag_lock = unsafe { csr::wrpll::gtx_tag_read() };
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*FIRST_GTX_INTERRUPT.lock() = false;
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*GTX_TAG_READY.lock() = true;
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}
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IRQ::MainTag => {
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*MAIN_TAG.lock() = unsafe { csr::wrpll::main_tag_read() };
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*MAIN_TAG_READY.lock() = true;
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}
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}
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}
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pub fn period_det_ready() -> bool {
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*PERIOD_DET_READY.lock()
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}
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pub fn phase_det_ready() -> bool {
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*GTX_TAG_READY.lock() && *MAIN_TAG_READY.lock()
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}
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pub fn get_period_error() -> i32 {
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// overflowing_sub can calculate the correct beating period when GTX_TAG roll over
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BEATING_PERIOD - ((*GTX_TAG.lock()).overflowing_sub(*LAST_GTX_TAG.lock()).0) as i32
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}
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pub fn get_phase_error() -> i32 {
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// unwrap tag difference
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let mut phase_error = (*MAIN_TAG.lock())
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.overflowing_sub(*GTX_TAG.lock())
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.0
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.rem_euclid(BEATING_PERIOD as u32) as i32;
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// mapping tags from [0, 2π] -> [-π, π]
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if phase_error > BEATING_HALFPERIOD {
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phase_error -= BEATING_PERIOD
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}
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phase_error
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}
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}
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pub fn helper_setup(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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unsafe {
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csr::wrpll::helper_reset_write(1);
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csr::helper_dcxo::bitbang_enable_write(1);
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csr::helper_dcxo::i2c_address_write(ADDRESS);
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}
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#[cfg(rtio_frequency = "125.0")]
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let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x058, 0, 0x0481458C94D); // 125Mhz*16383/16384
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setup(i2c::DCXO::Helper, h_hsdiv, h_lsdiv, h_fbdiv, timer)?;
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// Si549 maximum settling time for large frequency change.
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timer.delay_us(40_000);
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unsafe {
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csr::wrpll::helper_reset_write(0);
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csr::helper_dcxo::bitbang_enable_write(0);
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}
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info!("Helper Si549 started");
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Ok(())
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}
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pub fn interrupt_setup(interrupt_controller: &mut gic::InterruptController) {
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for id in IRQ_ID.iter() {
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// setup shared peripheral interrupts (SPI)
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interrupt_controller.enable(
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gic::InterruptId(*id),
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gic::CPUCore::Core0,
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gic::InterruptSensitivity::Edge,
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0,
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);
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}
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}
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fn set_irq(en: bool) {
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let val = if en { 1 } else { 0 };
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unsafe {
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csr::wrpll::gtx_tag_ev_enable_write(val);
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csr::wrpll::main_tag_ev_enable_write(val);
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}
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}
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/// set adpll using gateware i2c
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/// Note: disable main/helper i2c bitbang before using this function
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fn set_adpll(dcxo: i2c::DCXO, adpll: i32) -> Result<(), &'static str> {
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if adpll.abs() > ADPLL_MAX {
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return Err("adpll is too large");
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}
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match dcxo {
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i2c::DCXO::Main => unsafe {
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if csr::main_dcxo::bitbang_enable_read() == 1 {
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return Err("Main si549 bitbang mode is active when using gateware i2c");
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}
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while csr::main_dcxo::adpll_busy_read() == 1 {}
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csr::main_dcxo::i2c_address_write(ADDRESS);
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csr::main_dcxo::adpll_write(adpll as u32);
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csr::main_dcxo::adpll_stb_write(1);
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csr::main_dcxo::adpll_stb_write(0);
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if csr::main_dcxo::nack_read() == 1 {
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return Err("Main si549 failed to ack adpll write");
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}
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},
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#[cfg(has_wrpll)]
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i2c::DCXO::Helper => unsafe {
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if csr::helper_dcxo::bitbang_enable_read() == 1 {
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return Err("Helper si549 bitbang mode is active when using gateware i2c");
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}
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while csr::helper_dcxo::adpll_busy_read() == 1 {}
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csr::helper_dcxo::i2c_address_write(ADDRESS);
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csr::helper_dcxo::adpll_write(adpll as u32);
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csr::helper_dcxo::adpll_stb_write(1);
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csr::helper_dcxo::adpll_stb_write(0);
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if csr::helper_dcxo::nack_read() == 1 {
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return Err("Helper si549 failed to ack adpll write");
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}
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},
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};
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Ok(())
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}
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fn set_base_adpll(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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let count2adpll =
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|error: i32| (((error) as f64 * 1e6) / (0.0001164 * (1 << (TIMER_WIDTH - COUNTER_DIV)) as f64)) as i32;
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let (gtx_count, main_count, _helper_count) = get_freq_counts(timer);
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let mut base_adpll_lock = BASE_ADPLL.lock();
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*base_adpll_lock = count2adpll(gtx_count as i32 - main_count as i32);
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set_adpll(i2c::DCXO::Main, *base_adpll_lock)?;
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set_adpll(i2c::DCXO::Helper, *base_adpll_lock)?;
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Ok(())
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}
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fn get_freq_counts(timer: &mut GlobalTimer) -> (u32, u32, u32) {
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unsafe {
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csr::wrpll::frequency_counter_update_en_write(1);
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timer.delay_us(150_000); // 8ns << TIMER_WIDTH
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csr::wrpll::frequency_counter_update_en_write(0);
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let gtx = csr::wrpll::frequency_counter_counter_gtx0_rtio_rx_read();
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let main = csr::wrpll::frequency_counter_counter_sys_read();
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let helper = csr::wrpll::frequency_counter_counter_helper_read();
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(gtx, main, helper)
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}
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}
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fn reset_plls() -> Result<(), &'static str> {
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*H_INTEGRATOR.lock() = 0;
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*M_INTEGRATOR.lock() = 0;
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set_adpll(i2c::DCXO::Main, 0)?;
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set_adpll(i2c::DCXO::Helper, 0)?;
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Ok(())
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}
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fn clear_pending(interrupt: IRQ) {
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match interrupt {
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IRQ::GTXTag => unsafe { csr::wrpll::gtx_tag_ev_pending_write(1) },
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IRQ::MainTag => unsafe { csr::wrpll::main_tag_ev_pending_write(1) },
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}
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}
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pub fn interrupt_handler(interrupt: IRQ) {
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tag_collector::collect_tags(interrupt);
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if tag_collector::period_det_ready() {
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helper_pll().expect("failed to run helper DCXO PLL");
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tag_collector::clear_period_det_ready();
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}
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if tag_collector::phase_det_ready() {
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main_pll().expect("failed to run main DCXO PLL");
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tag_collector::clear_phase_det_ready();
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}
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clear_pending(interrupt);
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}
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pub fn helper_pll() -> Result<(), &'static str> {
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const H_KP: i32 = 2;
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const H_KI: f32 = 0.5;
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let period_err = tag_collector::get_period_error();
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let mut integrator_lock = H_INTEGRATOR.lock();
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*integrator_lock += (period_err as f32 * H_KI) as i32;
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let mut h_adpll = *BASE_ADPLL.lock() + period_err * H_KP + *integrator_lock;
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h_adpll = h_adpll.clamp(-ADPLL_MAX, ADPLL_MAX);
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set_adpll(i2c::DCXO::Helper, h_adpll)?;
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Ok(())
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}
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pub fn main_pll() -> Result<(), &'static str> {
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const M_KP: i32 = 12;
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const M_KI: i32 = 2;
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let phase_err = tag_collector::get_phase_error();
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let mut integrator_lock = M_INTEGRATOR.lock();
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*integrator_lock += phase_err * M_KI;
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let mut m_adpll = *BASE_ADPLL.lock() + phase_err * M_KP + *integrator_lock;
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m_adpll = m_adpll.clamp(-ADPLL_MAX, ADPLL_MAX);
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set_adpll(i2c::DCXO::Main, m_adpll)?;
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Ok(())
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}
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pub fn select_recovered_clock(rc: bool, timer: &mut GlobalTimer) {
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set_irq(false);
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if rc {
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tag_collector::reset();
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reset_plls().expect("failed to reset main and helper PLL");
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info!("warming up GTX CDR...");
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// gtx need a couple seconds for freq counter to read it properly
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timer.delay_us(20_000_000);
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set_base_adpll(timer).expect("failed to set base adpll");
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// clear gateware pending flag
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clear_pending(IRQ::GTXTag);
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clear_pending(IRQ::MainTag);
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set_irq(true);
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info!("WRPLL interrupt enabled");
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}
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}
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}
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@ -1,5 +1,7 @@
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use core::sync::atomic::{AtomicBool, Ordering};
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#[cfg(has_wrpll)]
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use libboard_artiq::si549;
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use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{asm, interrupt_handler, notify_spin_lock, regs::MPIDR, spin_lock_yield};
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use libregister::RegisterR;
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@ -12,16 +14,37 @@ extern "C" {
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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if MPIDR.read().cpu_id() == 1 {
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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asm!("b core1_restart");
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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// IRQ ID information at https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=D777grsNOem_mnEV7glhfg
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match MPIDR.read().cpu_id() {
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0 => match id.0 {
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61 => {
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#[cfg(has_wrpll)]
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si549::wrpll::interrupt_handler(si549::wrpll::IRQ::GTXTag);
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gic.end_interrupt(id);
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return;
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}
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62 => {
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#[cfg(has_wrpll)]
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si549::wrpll::interrupt_handler(si549::wrpll::IRQ::MainTag);
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gic.end_interrupt(id);
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return;
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}
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_ => {}
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},
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1 => {
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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asm!("b core1_restart");
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}
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}
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}
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_ => {}
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};
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stdio::drop_uart();
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println!("IRQ");
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loop {}
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@ -37,6 +37,8 @@ use libboard_artiq::{drtio_routing, drtioaux,
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pl::csr};
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#[cfg(feature = "target_kasli_soc")]
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use libboard_zynq::error_led::ErrorLED;
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#[cfg(has_wrpll)]
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use libboard_zynq::{gic::InterruptController, mpcore::RegisterBlock};
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use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer};
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use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
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use libregister::RegisterR;
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@ -739,6 +741,9 @@ pub extern "C" fn main_core0() -> i32 {
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let mut timer = GlobalTimer::start();
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#[cfg(has_wrpll)]
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let mut interrupt_controller = InterruptController::gic(RegisterBlock::mpcore());
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let buffer_logger = unsafe { logger::BufferLogger::new(&mut LOG_BUFFER[..]) };
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buffer_logger.set_uart_log_level(log::LevelFilter::Info);
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buffer_logger.register();
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@ -799,6 +804,11 @@ pub extern "C" fn main_core0() -> i32 {
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unsafe {
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csr::gt_drtio::txenable_write(0xffffffffu32 as _);
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}
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#[cfg(has_wrpll)]
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{
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si549::wrpll::helper_setup(&mut timer).expect("cannot initialize helper Si549");
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si549::wrpll::interrupt_setup(&mut interrupt_controller);
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}
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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@ -841,6 +851,9 @@ pub extern "C" fn main_core0() -> i32 {
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si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
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}
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#[cfg(has_wrpll)]
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si549::wrpll::select_recovered_clock(true, &mut timer);
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// Various managers created here, so when link is dropped, all DMA traces
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// are cleared out for a clean slate on subsequent connections,
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// without a manual intervention.
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@ -898,6 +911,8 @@ pub extern "C" fn main_core0() -> i32 {
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info!("uplink is down, switching to local oscillator clock");
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#[cfg(has_siphaser)]
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si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
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#[cfg(has_wrpll)]
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si549::wrpll::select_recovered_clock(false, &mut timer);
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}
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}
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Loading…
Reference in New Issue