M-Labs/artiq-zynq
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runtime/rtio_acp: change back to normal sequence.

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This commit is contained in:
pca006132 2020-08-11 13:33:31 +08:00
parent d12bf11de1
commit df44eab2bc
2 changed files with 26 additions and 39 deletions
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4
examples/blink_forever.py
View File

@ -10,5 +10,5 @@ class BlinkForever(EnvExperiment):
def run(self):
self.core.reset()
while True:
self.led0.pulse(100*ms)
delay(100*ms)
self.led0.pulse(490*ns)
delay(490*ns)

61
src/runtime/src/rtio_acp.rs
View File

@ -1,7 +1,6 @@
use cslice::{CSlice, AsCSlice};
use cslice::CSlice;
use vcell::VolatileCell;
use libcortex_a9::{asm, cache::dcci};
use log::debug;
use libcortex_a9::asm;
use crate::artiq_raise;
use core::sync::atomic::{fence, Ordering};
@ -55,8 +54,6 @@ pub extern fn init() {
csr::rtio_core::reset_write(1);
csr::rtio::engine_addr_base_write(&TRANSACTION_BUFFER as *const Transaction as u32);
csr::rtio::enable_write(1);
debug!("Set reply status");
TRANSACTION_BUFFER.reply_status.set(0x1000);
}
}
@ -107,6 +104,17 @@ unsafe fn process_exceptional_status(channel: i32, status: i32) {
pub extern fn output(target: i32, data: i32) {
unsafe {
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = 1;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[0] = data;
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
@ -119,28 +127,22 @@ pub extern fn output(target: i32, data: i32) {
if status != 0 {
process_exceptional_status(target >> 8, status);
}
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
// volatile are not used temporarily to allow the compiler to optimize better...
// probably would use it back later.
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = 1;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[0] = data;
fence(Ordering::SeqCst);
asm::sev();
dcci(&TRANSACTION_BUFFER.reply_status);
// asm::wfe();
// optimize cache...
// asm::wfe();
}
}
pub extern fn output_wide(target: i32, data: CSlice<i32>) {
unsafe {
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = data.len() as i8;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[..data.len()].copy_from_slice(data.as_ref());
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
@ -153,18 +155,6 @@ pub extern fn output_wide(target: i32, data: CSlice<i32>) {
if status != 0 {
process_exceptional_status(target >> 8, status);
}
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = data.len() as i8;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[..data.len()].copy_from_slice(data.as_ref());
fence(Ordering::SeqCst);
asm::sev();
dcci(&TRANSACTION_BUFFER.reply_status);
}
}
@ -179,7 +169,6 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
fence(Ordering::SeqCst);
asm::sev();
dcci(&TRANSACTION_BUFFER.reply_status);
let mut status;
loop {
@ -217,7 +206,6 @@ pub extern fn input_data(channel: i32) -> i32 {
fence(Ordering::SeqCst);
asm::sev();
dcci(&TRANSACTION_BUFFER.reply_status);
let mut status;
loop {
@ -252,7 +240,6 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
fence(Ordering::SeqCst);
asm::sev();
dcci(&TRANSACTION_BUFFER.reply_status);
let mut status;
loop {