M-Labs/artiq-zynq
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fix analyzer target for masters

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This commit is contained in:
spaqin 2023-05-22 15:32:49 +08:00
parent 6b9212525a
commit d51f86672a
2 changed files with 2 additions and 2 deletions
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2
src/gateware/kasli_soc.py
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@ -311,7 +311,7 @@ class GenericMaster(SoCCore):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")

2
src/gateware/zc706.py
View File

@ -320,7 +320,7 @@ class _MasterBase(SoCCore):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")