rtio_clocking: add error led support
* config functions return Result instead of being void
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@ -127,10 +127,6 @@ class GenericStandalone(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.submodules += SMAClkinForward(self.platform)
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self.rustc_cfg["has_si5324"] = None
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@ -219,10 +215,6 @@ class GenericMaster(SoCCore):
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self.submodules += SMAClkinForward(self.platform)
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -346,10 +338,6 @@ class GenericSatellite(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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@ -4,6 +4,8 @@ use embedded_hal::blocking::delay::DelayMs;
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use libasync::task;
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use libconfig::Config;
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use libboard_artiq::pl;
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#[cfg(feature = "target_kasli_soc")]
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use libboard_zynq::error_led::ErrorLED;
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#[cfg(has_si5324)]
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use libboard_zynq::i2c::I2c;
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#[cfg(has_si5324)]
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@ -69,7 +71,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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}
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fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
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fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) -> Result<()> {
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#[cfg(has_rtio_crg_clock_sel)]
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let clock_sel = match _clk {
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RtioClock::Ext0_Bypass => {
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@ -98,19 +100,14 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
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info!("RTIO PLL locked");
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} else {
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error!("RTIO PLL failed to lock");
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#[cfg(feature = "target_kasli_soc")]
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{
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unsafe {
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pl::csr::error_led::out_write(1);
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}
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soft_panic();
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// try "soft" panic
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}
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return Err("RTIO PLL failed to lock");
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}
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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Ok(())
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}
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#[cfg(has_drtio)]
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@ -126,7 +123,7 @@ fn init_drtio(timer: &mut GlobalTimer)
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}
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#[cfg(has_si5324)]
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fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) -> Result<()> {
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let (si5324_settings, si5324_ref_input) = match clk {
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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@ -241,7 +238,7 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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)
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}
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};
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer)
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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@ -251,26 +248,39 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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{
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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let si5324_ext_input = si5324::Input::Ckin1;
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match clk {
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RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
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let res = match clk {
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RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer),
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_ => setup_si5324(i2c, timer, clk),
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}
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if res.is_err() {
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soft_panic();
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}
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}
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#[cfg(has_drtio)]
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init_drtio(timer);
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init_rtio(timer, clk);
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if init_rtio(timer, clk).is_err() {
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soft_panic();
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}
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}
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#[cfg(feature = "target_kasli_soc")]
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fn soft_panic() {
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error!("Error setting up RTIO clocking. Only mgmt interface will be available.");
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// start mgmt service but nothing else
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let cfg = match Config::new() {
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Ok(cfg) => cfg,
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Err(_) => Config::new_dummy()
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};
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mgmt::start(cfg);
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#[cfg(feature = "target_kasli_soc")]
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{
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let mut err_led = ErrorLED::error_led();
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err_led.toggle(true);
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}
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loop {
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task::block_on(task::r#yield());
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}
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