diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index 3e871c0..1c95a37 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -127,10 +127,6 @@ class GenericStandalone(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
-        self.submodules.error_led = gpio.GPIOOut(Cat(
-            self.platform.request("error_led")))
-        self.csr_devices.append("error_led")
-
         self.submodules += SMAClkinForward(self.platform)
 
         self.rustc_cfg["has_si5324"] = None
@@ -219,10 +215,6 @@ class GenericMaster(SoCCore):
 
         self.submodules += SMAClkinForward(self.platform)
 
-        self.submodules.error_led = gpio.GPIOOut(Cat(
-            self.platform.request("error_led")))
-        self.csr_devices.append("error_led")
-
         data_pads = [platform.request("sfp", i) for i in range(4)]
 
         self.submodules.drtio_transceiver = gtx_7series.GTX(
@@ -346,10 +338,6 @@ class GenericSatellite(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
-        self.submodules.error_led = gpio.GPIOOut(Cat(
-            self.platform.request("error_led")))
-        self.csr_devices.append("error_led")
-
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs
index 60e960f..e1b9a03 100644
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@@ -4,6 +4,8 @@ use embedded_hal::blocking::delay::DelayMs;
 use libasync::task;
 use libconfig::Config;
 use libboard_artiq::pl;
+#[cfg(feature = "target_kasli_soc")]
+use libboard_zynq::error_led::ErrorLED;
 #[cfg(has_si5324)]
 use libboard_zynq::i2c::I2c;
 #[cfg(has_si5324)]
@@ -69,7 +71,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
 }
 
 
-fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
+fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) -> Result<()> {
     #[cfg(has_rtio_crg_clock_sel)]
     let clock_sel = match _clk {
         RtioClock::Ext0_Bypass => { 
@@ -98,19 +100,14 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
         info!("RTIO PLL locked");
     } else {
         error!("RTIO PLL failed to lock");
-        #[cfg(feature = "target_kasli_soc")]
-        {
-            unsafe {
-                pl::csr::error_led::out_write(1);
-            }
-            soft_panic();
-            // try "soft" panic
-        }
+        return Err("RTIO PLL failed to lock");
     }
 
     unsafe {
         pl::csr::rtio_core::reset_phy_write(1);
     }
+
+    Ok(())
 }
 
 #[cfg(has_drtio)]
@@ -126,7 +123,7 @@ fn init_drtio(timer: &mut GlobalTimer)
 }
 
 #[cfg(has_si5324)]
-fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
+fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) -> Result<()> {
     let (si5324_settings, si5324_ref_input) = match clk {
         RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
             info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
@@ -241,7 +238,7 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
             )
         }
     };
-    si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
+    si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer)
 }
 
 pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
@@ -251,26 +248,39 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
     {
         let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
         let si5324_ext_input = si5324::Input::Ckin1;
-        match clk {
-            RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
+        let res = match clk {
+            RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer),
             _ => setup_si5324(i2c, timer, clk),
         }
+        if res.is_err() {
+            soft_panic();
+        }
     }
     #[cfg(has_drtio)]
     init_drtio(timer);
 
-    init_rtio(timer, clk);
+    if init_rtio(timer, clk).is_err() {
+        soft_panic();
+    }
 
 }
 
-#[cfg(feature = "target_kasli_soc")]
+
 fn soft_panic() {
+    error!("Error setting up RTIO clocking. Only mgmt interface will be available.");
     // start mgmt service but nothing else
     let cfg = match Config::new() {
         Ok(cfg) => cfg,
         Err(_) => Config::new_dummy()
     };
     mgmt::start(cfg);
+
+    #[cfg(feature = "target_kasli_soc")]
+    {
+        let mut err_led = ErrorLED::error_led();
+        err_led.toggle(true);
+    }
+
     loop {
         task::block_on(task::r#yield());
     }