freq counter fw: fix counts formula & remove delay
parent
7b97d30a43
commit
cf3f5dfcfa
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@ -334,8 +334,8 @@ pub mod wrpll {
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const BEATING_PERIOD: i32 = 0x8000;
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const BEATING_HALFPERIOD: i32 = 0x4000;
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const TIMER_WIDTH: u32 = 24;
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const COUNTER_DIV: u32 = 2;
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const COUNTER_WIDTH: u32 = 24;
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const FREQ_DIV: u32 = 2;
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const KP: i32 = 6;
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const KI: i32 = 2;
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@ -435,11 +435,11 @@ pub mod wrpll {
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}
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/// To get within capture range
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fn set_base_adpll(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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fn set_base_adpll() -> Result<(), &'static str> {
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let count2adpll =
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|error: i32| (((error) as f64 * 1e6) / (0.0001164 * (1 << (TIMER_WIDTH - COUNTER_DIV)) as f64)) as i32;
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|error: i32| ((error as f64 * FREQ_DIV as f64 * 1e6) / (0.0001164 * (1 << COUNTER_WIDTH) as f64)) as i32;
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let (ref_count, main_count) = get_freq_counts(timer);
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let (ref_count, main_count) = get_freq_counts();
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let mut base_adpll_lock = BASE_ADPLL.lock();
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*base_adpll_lock = count2adpll(ref_count as i32 - main_count as i32);
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set_adpll(i2c::DCXO::Main, *base_adpll_lock)?;
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@ -448,10 +448,10 @@ pub mod wrpll {
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Ok(())
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}
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fn get_freq_counts(timer: &mut GlobalTimer) -> (u32, u32) {
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fn get_freq_counts() -> (u32, u32) {
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unsafe {
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csr::wrpll::frequency_counter_update_write(1);
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timer.delay_us(150_000); // 8ns << TIMER_WIDTH
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while csr::wrpll::frequency_counter_busy_read() == 1 {}
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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@ -644,7 +644,7 @@ pub mod wrpll {
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if rc {
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tag_collector::reset();
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reset_plls(timer).expect("failed to reset main and helper PLL");
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set_base_adpll(timer).expect("failed to set base adpll");
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set_base_adpll().expect("failed to set base adpll");
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// clear gateware pending flag
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clear_pending(ISR::RefTag);
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