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freq counter gw: cleanup

morgan 2024-04-09 12:10:34 +08:00
parent fa5765383f
commit 7b97d30a43
1 changed files with 24 additions and 15 deletions
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39
src/gateware/wrpll.py
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@ -7,12 +7,13 @@ from ddmtd import DDMTDSampler, DDMTD
from si549 import Si549
class FrequencyCounter(Module, AutoCSR):
def __init__(self, domains, counter_width=24, freq_divider=2):
def __init__(self, domains, counter_width=24, freq_div=2):
self.update = CSR()
self.busy = CSRStatus()
counter_reset = Signal()
counter_stb = Signal()
timer = Signal(max=2**counter_width)
timer = Signal(counter_width)
# # #
@ -27,6 +28,7 @@ class FrequencyCounter(Module, AutoCSR):
)
)
fsm.act("COUNTING",
self.busy.status.eq(1),
If(timer != 0,
NextValue(timer, timer - 1)
).Else(
@ -40,30 +42,37 @@ class FrequencyCounter(Module, AutoCSR):
counter_csr = CSRStatus(counter_width, name=name)
setattr(self, name, counter_csr)
counter = Signal(max=1 << freq_divider)
divided_counter = Signal(counter_width)
counter = Signal(max=freq_div)
result = Signal(counter_width)
# # #
stb_ps = PulseSynchronizer(domain, "sys")
self.submodules += stb_ps
reset_ps = PulseSynchronizer("sys", domain)
stb_ps = PulseSynchronizer("sys", domain)
self.submodules +=[
reset_ps,
stb_ps
]
self.sync +=[
reset_ps.i.eq(counter_reset),
stb_ps.i.eq(counter_stb)
]
sync_domain = getattr(self.sync, domain)
sync_domain += [
If(counter != 0,
stb_ps.i.eq(0),
counter.eq(counter - 1)
).Else(
stb_ps.i.eq(1),
counter.eq((1 << freq_divider) - 1)
)
result.eq(result + 1),
counter.eq(freq_div - 1)
),
If(reset_ps.o,
counter.eq(0),
result.eq(0)
),
If(stb_ps.o, counter_csr.status.eq(result))
]
self.sync += [
If(counter_reset, divided_counter.eq(0)),
If(stb_ps.o, divided_counter.eq(divided_counter + 1)),
If(counter_stb, counter_csr.status.eq(divided_counter))
]
class SkewTester(Module, AutoCSR):
def __init__(self, rx_synchronizer):