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freq counter fw: fix counts formula & remove delay

morgan 2024-04-09 12:11:42 +08:00
parent 7b97d30a43
commit cf3f5dfcfa
1 changed files with 8 additions and 8 deletions
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16
src/libboard_artiq/src/si549.rs
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@ -334,8 +334,8 @@ pub mod wrpll {
const BEATING_PERIOD: i32 = 0x8000;
const BEATING_HALFPERIOD: i32 = 0x4000;
const TIMER_WIDTH: u32 = 24;
const COUNTER_DIV: u32 = 2;
const COUNTER_WIDTH: u32 = 24;
const FREQ_DIV: u32 = 2;
const KP: i32 = 6;
const KI: i32 = 2;
@ -435,11 +435,11 @@ pub mod wrpll {
}
/// To get within capture range
fn set_base_adpll(timer: &mut GlobalTimer) -> Result<(), &'static str> {
fn set_base_adpll() -> Result<(), &'static str> {
let count2adpll =
|error: i32| (((error) as f64 * 1e6) / (0.0001164 * (1 << (TIMER_WIDTH - COUNTER_DIV)) as f64)) as i32;
|error: i32| ((error as f64 * FREQ_DIV as f64 * 1e6) / (0.0001164 * (1 << COUNTER_WIDTH) as f64)) as i32;
let (ref_count, main_count) = get_freq_counts(timer);
let (ref_count, main_count) = get_freq_counts();
let mut base_adpll_lock = BASE_ADPLL.lock();
*base_adpll_lock = count2adpll(ref_count as i32 - main_count as i32);
set_adpll(i2c::DCXO::Main, *base_adpll_lock)?;
@ -448,10 +448,10 @@ pub mod wrpll {
Ok(())
}
fn get_freq_counts(timer: &mut GlobalTimer) -> (u32, u32) {
fn get_freq_counts() -> (u32, u32) {
unsafe {
csr::wrpll::frequency_counter_update_write(1);
timer.delay_us(150_000); // 8ns << TIMER_WIDTH
while csr::wrpll::frequency_counter_busy_read() == 1 {}
#[cfg(wrpll_ref_clk = "GT_CDR")]
let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
@ -644,7 +644,7 @@ pub mod wrpll {
if rc {
tag_collector::reset();
reset_plls(timer).expect("failed to reset main and helper PLL");
set_base_adpll(timer).expect("failed to set base adpll");
set_base_adpll().expect("failed to set base adpll");
// clear gateware pending flag
clear_pending(ISR::RefTag);