zc706 nist clock: started rtio channel changes
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@ -163,10 +163,6 @@ class NIST_CLOCK(ZC706):
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rtio_channels = []
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led_33", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(16):
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for i in range(16):
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if i % 4 == 3:
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if i % 4 == 3:
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@ -183,16 +179,42 @@ class NIST_CLOCK(ZC706):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# todo: figure out pins for that on zc706
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# phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
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# self.submodules += phy
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# rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# could check the LED #
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phy = ttl_simple.Output(platform.request("user_led_33", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi2.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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for i in range(3):
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for i in range(3):
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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phy, ififo_depth=128))
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# todo check sdcard spi pins on zc706 (if applicable)
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# phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
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# self.submodules += phy
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# rtio_channels.append(rtio.Channel.from_phy(
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# phy, ififo_depth=4))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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