kasli soc: refactor clock synth
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4f34a7c6d0
commit
945a9f1c47
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@ -47,6 +47,19 @@ eem_iostandard_dict = {
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def eem_iostandard(eem):
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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return IOStandard(eem_iostandard_dict[eem])
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class ClockSynthesis(Module):
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def __init__(self, platform):
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self.se = Signal()
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clk_synth = platform.request("cdr_clk_clean_fabric")
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=self.se
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),
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]
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class SMAClkinForward(Module):
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class SMAClkinForward(Module):
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def __init__(self, platform):
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def __init__(self, platform):
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@ -120,24 +133,10 @@ class GenericStandalone(SoCCore):
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self.config["HW_REV"] = description["hw_rev"]
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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clk_synth_se_buf = Signal()
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clk_synth_se_buf = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("BUFG", i_I=self.clk_synth.se, o_O=clk_synth_se_buf)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
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),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
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]
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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