From 945a9f1c47bc68be2bffeb588d44a46cc5631200 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 7 Mar 2024 13:11:41 +0800 Subject: [PATCH] kasli soc: refactor clock synth --- src/gateware/kasli_soc.py | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 25e9c04..716501e 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -47,6 +47,19 @@ eem_iostandard_dict = { def eem_iostandard(eem): return IOStandard(eem_iostandard_dict[eem]) +class ClockSynthesis(Module): + def __init__(self, platform): + self.se = Signal() + + clk_synth = platform.request("cdr_clk_clean_fabric") + platform.add_period_constraint(clk_synth.p, 8.0) + + self.specials += [ + Instance("IBUFGDS", + p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", + i_I=clk_synth.p, i_IB=clk_synth.n, o_O=self.se + ), + ] class SMAClkinForward(Module): def __init__(self, platform): @@ -120,24 +133,10 @@ class GenericStandalone(SoCCore): self.config["HW_REV"] = description["hw_rev"] - - self.submodules += SMAClkinForward(self.platform) - - self.config["HAS_SI5324"] = None - self.config["SI5324_SOFT_RESET"] = None - - clk_synth = platform.request("cdr_clk_clean_fabric") - clk_synth_se = Signal() + self.submodules.clk_synth = ClockSynthesis(self.platform) clk_synth_se_buf = Signal() - platform.add_period_constraint(clk_synth.p, 8.0) + self.specials += Instance("BUFG", i_I=self.clk_synth.se, o_O=clk_synth_se_buf) - self.specials += [ - Instance("IBUFGDS", - p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", - i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se - ), - Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf), - ] fix_serdes_timing_path(platform) self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq) self.config["CLOCK_FREQUENCY"] = int(clk_freq)