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fix freq counter need long delay to work

This commit is contained in:
morgan 2024-03-27 12:44:03 +08:00
parent 3a76f207e1
commit 8eeec0bae8
1 changed files with 16 additions and 9 deletions
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25
src/gateware/wrpll.py
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@ -14,9 +14,17 @@ class FrequencyCounter(Module, AutoCSR):
setattr(self, name, counter) setattr(self, name, counter)
self.update_en = CSRStorage() self.update_en = CSRStorage()
# # #
timer = Signal(counter_width) timer = Signal(counter_width)
timer_tick = Signal() timer_tick = Signal()
self.sync += Cat(timer, timer_tick).eq(timer + 1) self.sync +=[
If(self.update_en.storage,
Cat(timer, timer_tick).eq(timer + 1)
).Else(
Cat(timer, timer_tick).eq(0)
)
]
for domain in domains: for domain in domains:
sync_domain = getattr(self.sync, domain) sync_domain = getattr(self.sync, domain)
@ -30,18 +38,17 @@ class FrequencyCounter(Module, AutoCSR):
divided_sys_r = Signal() divided_sys_r = Signal()
divided_tick = Signal() divided_tick = Signal()
self.sync += divided_sys_r.eq(divided_sys) self.sync += [
self.comb += divided_tick.eq(divided_sys & ~divided_sys_r) divided_sys_r.eq(divided_sys),
divided_tick.eq(divided_sys & ~divided_sys_r)
]
counter = Signal(counter_width) counter = Signal(counter_width)
counter_csr = getattr(self, "counter_" + domain) counter_csr = getattr(self, "counter_" + domain)
self.sync += [ self.sync += [
If(timer_tick, If(timer_tick, counter_csr.status.eq(counter)),
If(self.update_en.storage, counter_csr.status.eq(counter)), If(divided_tick, counter.eq(counter + 1)),
counter.eq(0), If(~self.update_en.storage, counter.eq(0)),
).Else(
If(divided_tick, counter.eq(counter + 1))
)
] ]
class SkewTester(Module, AutoCSR): class SkewTester(Module, AutoCSR):