From 8eeec0bae8af9ce5cb7b5822af5f3e24707362d8 Mon Sep 17 00:00:00 2001 From: morgan Date: Wed, 27 Mar 2024 12:44:03 +0800 Subject: [PATCH] fix freq counter need long delay to work --- src/gateware/wrpll.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/src/gateware/wrpll.py b/src/gateware/wrpll.py index 268bda1..404d41c 100644 --- a/src/gateware/wrpll.py +++ b/src/gateware/wrpll.py @@ -14,9 +14,17 @@ class FrequencyCounter(Module, AutoCSR): setattr(self, name, counter) self.update_en = CSRStorage() + # # # + timer = Signal(counter_width) timer_tick = Signal() - self.sync += Cat(timer, timer_tick).eq(timer + 1) + self.sync +=[ + If(self.update_en.storage, + Cat(timer, timer_tick).eq(timer + 1) + ).Else( + Cat(timer, timer_tick).eq(0) + ) + ] for domain in domains: sync_domain = getattr(self.sync, domain) @@ -30,18 +38,17 @@ class FrequencyCounter(Module, AutoCSR): divided_sys_r = Signal() divided_tick = Signal() - self.sync += divided_sys_r.eq(divided_sys) - self.comb += divided_tick.eq(divided_sys & ~divided_sys_r) + self.sync += [ + divided_sys_r.eq(divided_sys), + divided_tick.eq(divided_sys & ~divided_sys_r) + ] counter = Signal(counter_width) counter_csr = getattr(self, "counter_" + domain) self.sync += [ - If(timer_tick, - If(self.update_en.storage, counter_csr.status.eq(counter)), - counter.eq(0), - ).Else( - If(divided_tick, counter.eq(counter + 1)) - ) + If(timer_tick, counter_csr.status.eq(counter)), + If(divided_tick, counter.eq(counter + 1)), + If(~self.update_en.storage, counter.eq(0)), ] class SkewTester(Module, AutoCSR):