freq counter gw: cleanup
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@ -7,12 +7,13 @@ from ddmtd import DDMTDSampler, DDMTD
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from si549 import Si549
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, domains, counter_width=24, freq_divider=2):
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def __init__(self, domains, counter_width=24, freq_div=2):
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self.update = CSR()
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self.busy = CSRStatus()
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counter_reset = Signal()
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counter_stb = Signal()
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timer = Signal(max=2**counter_width)
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timer = Signal(counter_width)
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# # #
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@ -27,6 +28,7 @@ class FrequencyCounter(Module, AutoCSR):
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)
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)
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fsm.act("COUNTING",
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self.busy.status.eq(1),
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If(timer != 0,
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NextValue(timer, timer - 1)
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).Else(
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@ -40,30 +42,37 @@ class FrequencyCounter(Module, AutoCSR):
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counter_csr = CSRStatus(counter_width, name=name)
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setattr(self, name, counter_csr)
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counter = Signal(max=1 << freq_divider)
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divided_counter = Signal(counter_width)
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counter = Signal(max=freq_div)
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result = Signal(counter_width)
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# # #
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stb_ps = PulseSynchronizer(domain, "sys")
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self.submodules += stb_ps
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reset_ps = PulseSynchronizer("sys", domain)
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stb_ps = PulseSynchronizer("sys", domain)
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self.submodules +=[
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reset_ps,
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stb_ps
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]
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self.sync +=[
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reset_ps.i.eq(counter_reset),
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stb_ps.i.eq(counter_stb)
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]
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sync_domain = getattr(self.sync, domain)
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sync_domain += [
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If(counter != 0,
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stb_ps.i.eq(0),
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counter.eq(counter - 1)
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).Else(
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stb_ps.i.eq(1),
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counter.eq((1 << freq_divider) - 1)
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)
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result.eq(result + 1),
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counter.eq(freq_div - 1)
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),
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If(reset_ps.o,
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counter.eq(0),
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result.eq(0)
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),
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If(stb_ps.o, counter_csr.status.eq(result))
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]
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self.sync += [
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If(counter_reset, divided_counter.eq(0)),
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If(stb_ps.o, divided_counter.eq(divided_counter + 1)),
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If(counter_stb, counter_csr.status.eq(divided_counter))
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]
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class SkewTester(Module, AutoCSR):
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def __init__(self, rx_synchronizer):
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