freq counter gw: refactor but still had bugs

src/gateware/wrpll.py

@@ -7,7 +7,7 @@ from ddmtd import DDMTDSampler, DDMTD
 from si549 import Si549
 
 class FrequencyCounter(Module, AutoCSR):
-    def __init__(self, domains, counter_width=24):
+    def __init__(self, domains, counter_width=24, freq_divider=2):
         self.update = CSR()
 
         counter_reset = Signal()
@@ -36,28 +36,33 @@ class FrequencyCounter(Module, AutoCSR):
         )
 
         for domain in domains:
-            divider = Signal(2)
-            divided_sys = Signal()
-            divided_sys_r = Signal()
-            rising = Signal()
-
             name = "counter_" + domain
             counter_csr = CSRStatus(counter_width, name=name)
             setattr(self, name, counter_csr)
-            counter = Signal(counter_width)
+
+            counter = Signal(max=1 << freq_divider)
+            divided_counter = Signal(counter_width)
+
+            # # #
+            
+            stb_ps = PulseSynchronizer(domain, "sys")
+            self.submodules += stb_ps
 
             sync_domain = getattr(self.sync, domain)
-            sync_domain += divider.eq(divider + 1)
-            self.specials += MultiReg(divider[-1], divided_sys)
-            self.sync += [
-                divided_sys_r.eq(divided_sys),
-                rising.eq(divided_sys & ~divided_sys_r)
+            sync_domain += [
+                If(counter != 0,
+                    stb_ps.i.eq(0),
+                    counter.eq(counter - 1)
+                ).Else(
+                    stb_ps.i.eq(1),
+                    counter.eq((1 << freq_divider) - 1)
+                )
             ]
 
             self.sync += [
-                If(counter_reset, counter.eq(0)),
-                If(rising, counter.eq(counter + 1)),
-                If(counter_stb, counter_csr.status.eq(counter))
+                If(counter_reset, divided_counter.eq(0)),
+                If(stb_ps.o, divided_counter.eq(divided_counter + 1)),
+                If(counter_stb, counter_csr.status.eq(divided_counter))
             ]
 
 class SkewTester(Module, AutoCSR):
@@ -85,6 +90,7 @@ class SkewTester(Module, AutoCSR):
 
 class WRPLL(Module, AutoCSR):
     def __init__(self, platform, cd_ref, main_clk_se, COUNTER_BIT=32):
+        self.refclk_reset = CSRStatus()
         self.helper_reset = CSRStorage(reset=1)
         self.ref_tag = CSRStatus(COUNTER_BIT)
         self.main_tag = CSRStatus(COUNTER_BIT)
@@ -98,6 +104,8 @@ class WRPLL(Module, AutoCSR):
 
         # # #
 
+        self.sync += self.refclk_reset.status.eq(cd_ref.rst)
+
         self.submodules.main_dcxo = Si549(platform.request("ddmtd_main_dcxo_i2c"))
         self.submodules.helper_dcxo = Si549(platform.request("ddmtd_helper_dcxo_i2c"))