M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests 1 Releases Wiki Activity

support absence of gateware RTIO clock selection mux
All checks were successful
Hydra zc706-hitl-tests Hydra build #130237 of artiq:zynq:zc706-hitl-tests
Details

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2021-02-15 21:41:30 +08:00
parent 8815f76114
commit 506c741238
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/gateware/zc706.py
View File

@ -83,6 +83,7 @@ class ZC706(SoCCore):
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
self.csr_devices.append("rtio_crg")
self.rustc_cfg["has_rtio_crg_clock_sel"] = None
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_false_path_constraints(
self.ps7.cd_sys.clk,

1
src/runtime/src/main.rs
View File

@ -108,6 +108,7 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
loop {
unsafe {
pl::csr::rtio_crg::pll_reset_write(1);
#[cfg(has_rtio_crg_clock_sel)]
pl::csr::rtio_crg::clock_sel_write(clock_sel);
pl::csr::rtio_crg::pll_reset_write(0);
}