From 506c7412383e5ef80daab22938c70eea44ee82a3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 15 Feb 2021 21:41:30 +0800 Subject: [PATCH] support absence of gateware RTIO clock selection mux --- src/gateware/zc706.py | 1 + src/runtime/src/main.rs | 1 + 2 files changed, 2 insertions(+) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 8731456..766cab5 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -83,6 +83,7 @@ class ZC706(SoCCore): self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) self.csr_devices.append("rtio_crg") + self.rustc_cfg["has_rtio_crg_clock_sel"] = None self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) self.platform.add_false_path_constraints( self.ps7.cd_sys.clk, diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index e846ae4..c27bba7 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -108,6 +108,7 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) { loop { unsafe { pl::csr::rtio_crg::pll_reset_write(1); + #[cfg(has_rtio_crg_clock_sel)] pl::csr::rtio_crg::clock_sel_write(clock_sel); pl::csr::rtio_crg::pll_reset_write(0); }