kasli_soc: add error_led
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@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from artiq.coredevice import jsondesc
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware import rtio, eem_7series
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@ -126,6 +127,10 @@ class GenericStandalone(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.submodules += SMAClkinForward(self.platform)
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self.submodules += SMAClkinForward(self.platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_si5324"] = None
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@ -214,6 +219,10 @@ class GenericMaster(SoCCore):
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self.submodules += SMAClkinForward(self.platform)
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self.submodules += SMAClkinForward(self.platform)
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -337,6 +346,10 @@ class GenericSatellite(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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