diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index d45bfc4..3e871c0 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import kasli_soc
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
+from misoc.cores import gpio
 
 from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
@@ -126,6 +127,10 @@ class GenericStandalone(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.submodules.error_led = gpio.GPIOOut(Cat(
+            self.platform.request("error_led")))
+        self.csr_devices.append("error_led")
+
         self.submodules += SMAClkinForward(self.platform)
 
         self.rustc_cfg["has_si5324"] = None
@@ -214,6 +219,10 @@ class GenericMaster(SoCCore):
 
         self.submodules += SMAClkinForward(self.platform)
 
+        self.submodules.error_led = gpio.GPIOOut(Cat(
+            self.platform.request("error_led")))
+        self.csr_devices.append("error_led")
+
         data_pads = [platform.request("sfp", i) for i in range(4)]
 
         self.submodules.drtio_transceiver = gtx_7series.GTX(
@@ -337,6 +346,10 @@ class GenericSatellite(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.submodules.error_led = gpio.GPIOOut(Cat(
+            self.platform.request("error_led")))
+        self.csr_devices.append("error_led")
+
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")