M-Labs/artiq-zynq
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disabled adding axi slave/mem

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drtioauxcontroller uses AXI rather than Wishbone
still won't compile - unresolved clock domain error
This commit is contained in:
mwojcik 2021-08-06 15:25:59 +02:00
parent ae86bbb76e
commit 118893c0b2
1 changed files with 6 additions and 2 deletions
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8
src/gateware/zc706.py
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@ -317,7 +317,9 @@ class Master(ZC706):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
# currently removed - DRTIOAuxController works with Wishbone
# while the board supports AXI
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtio", drtio_csr_group)
@ -421,7 +423,9 @@ class Satellite(ZC706):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
# currently removed - DRTIOAuxController works with Wishbone
# while the board supports AXI
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group)