From 118893c0b26116719ee822f63cbae979543d6d25 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 6 Aug 2021 15:25:59 +0200 Subject: [PATCH] disabled adding axi slave/mem drtioauxcontroller uses AXI rather than Wishbone still won't compile - unresolved clock domain error --- src/gateware/zc706.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 68c9ff8..d4b25cf 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -317,7 +317,9 @@ class Master(ZC706): self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800*i - self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) + # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) + # currently removed - DRTIOAuxController works with Wishbone + # while the board supports AXI self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) @@ -421,7 +423,9 @@ class Satellite(ZC706): self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800*i - self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) + # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) + # currently removed - DRTIOAuxController works with Wishbone + # while the board supports AXI self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group)