M-Labs/artiq-zynq
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zynq_clocking: export clk switch status

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mwojcik 2023-02-14 11:14:27 +08:00
parent e6b9d5ebcb
commit 062fa8e65d
1 changed files with 10 additions and 3 deletions
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13
src/gateware/zynq_clocking.py
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@ -70,6 +70,8 @@ class SYSCRG(Module, AutoCSR):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.current_clock = CSRStatus()
self.cd_sys.clk.attr.add("keep") self.cd_sys.clk.attr.add("keep")
self.cd_bootstrap.clk.attr.add("keep") self.cd_bootstrap.clk.attr.add("keep")
@ -87,9 +89,10 @@ class SYSCRG(Module, AutoCSR):
else: else:
self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
platform.add_period_constraint(self.cd_bootstrap.clk, 8.0)
self.specials += [ self.specials += [
Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk),
# Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_sys.clk),
Instance("PLLE2_ADV", Instance("PLLE2_ADV",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
p_BANDWIDTH="HIGH", p_BANDWIDTH="HIGH",
@ -99,9 +102,11 @@ class SYSCRG(Module, AutoCSR):
i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
# VCO @ 1.5GHz when using 125MHz input # VCO @ 1.5GHz when using 125MHz input
# FCLK on startup is ~42MHz, VCO below minimum
# do not use SYS before FCLK is configured from PS
p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=fb_clk, i_CLKFBIN=fb_clk,
i_RST=self.clk_sw_fsm.o_reset, i_RST=self.clk_sw_fsm.o_reset | ~ps7.fclk.reset_n[0],
o_CLKFBOUT=fb_clk, o_CLKFBOUT=fb_clk,
@ -113,6 +118,8 @@ class SYSCRG(Module, AutoCSR):
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0]), AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0] | ~pll_locked)
] ]
platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)
self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)