From 062fa8e65d038b17a40f286ddd19366875df662d Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 14 Feb 2023 11:14:27 +0800 Subject: [PATCH] zynq_clocking: export clk switch status --- src/gateware/zynq_clocking.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index baed5e8..f596e04 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -70,6 +70,8 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.current_clock = CSRStatus() + self.cd_sys.clk.attr.add("keep") self.cd_bootstrap.clk.attr.add("keep") @@ -86,10 +88,11 @@ class SYSCRG(Module, AutoCSR): self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) else: self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) + + platform.add_period_constraint(self.cd_bootstrap.clk, 8.0) self.specials += [ Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), - # Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_sys.clk), Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_BANDWIDTH="HIGH", @@ -99,9 +102,11 @@ class SYSCRG(Module, AutoCSR): i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, # VCO @ 1.5GHz when using 125MHz input + # FCLK on startup is ~42MHz, VCO below minimum + # do not use SYS before FCLK is configured from PS p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, - i_RST=self.clk_sw_fsm.o_reset, + i_RST=self.clk_sw_fsm.o_reset | ~ps7.fclk.reset_n[0], o_CLKFBOUT=fb_clk, @@ -113,6 +118,8 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0]), + AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0] | ~pll_locked) ] platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) + + self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)