58 lines
1.8 KiB
Markdown
58 lines
1.8 KiB
Markdown
HeavyX
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======
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A FPGA SoC framework embracing cutting-edge open source technologies (nMigen, Yosys, SymbiFlow, Minerva, Nix, Rust).
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This is work in progress!
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"Hello World" SoC demo
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----------------------
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Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain.
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* Everything written in nMigen (https://github.com/m-labs/nmigen/).
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* RISC-V 32-bit pipelined core (Minerva by Lambdaconcept).
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* 100MHz clock frequency.
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* Runs a Rust "hello world" program.
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Use nixpkgs 19.03. If you are unfamiliar with Nix and just installed it on another (non-NixOS) distribution, simply run:
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```
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$ nix-channel --remove nixpkgs
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$ nix-channel --add https://nixos.org/channels/nixos-19.03 nixpkgs
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$ nix-channel --update
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```
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Optional: set up the M-Labs key and binary substituter for Nix (otherwise Nix will recompile LLVM, rustc, etc. on your machine).
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Create the file ``~/.config/nix/nix.conf`` with the following contents:
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```
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substituters = https://cache.nixos.org https://nixbld.m-labs.hk
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trusted-public-keys = cache.nixos.org-1:6NCHdD59X431o0gWypbMrAURkbJ16ZPMQFGspcDShjY= nixbld.m-labs.hk-1:5aSRVA5b320xbNvu30tqxVPXpld73bhtOeH6uAjRyHc=
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```
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Run ``nix-build -A simplesoc_ecp5 release.nix``
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You can also build manually and use your distribution's packages, but YMMV.
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Bypass the ispCLOCK device using the jumpers on your board.
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Create a ``versa.cfg`` file with:
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```
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 5000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043
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```
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Load the bitstream ``openocd -f versa.cfg -c "transport select jtag; init; svf result/top.svf; exit"``.
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Watch the UART output at 115200bps.
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Questions, comments: https://forum.m-labs.hk/ or IRC #m-labs on Freenode.
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