update README
This commit is contained in:
parent
0bb4a0da46
commit
b93ee35a7d
@ -3,6 +3,8 @@ HeavyX
|
||||
|
||||
A FPGA SoC framework embracing cutting-edge open source technologies (nMigen, Yosys, SymbiFlow, Minerva, Nix, Rust).
|
||||
|
||||
This is work in progress!
|
||||
|
||||
"Hello World" SoC demo
|
||||
----------------------
|
||||
|
||||
@ -38,4 +40,4 @@ Load the bitstream ``openocd -f versa.cfg -c "transport select jtag; init; svf r
|
||||
|
||||
Watch the UART output at 115200bps.
|
||||
|
||||
Questions, comments: https://forum.m-labs.hk/
|
||||
Questions, comments: https://forum.m-labs.hk/ or IRC #m-labs on Freenode.
|
||||
|
Loading…
Reference in New Issue
Block a user