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README: add some details

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Sebastien Bourdeauducq 2019-06-24 18:25:44 +08:00
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README.md
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@ -8,7 +8,11 @@ This is work in progress!
"Hello World" SoC demo "Hello World" SoC demo
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Softcore RISC-V system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain. Runs a Rust "hello world" program. Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain.
* RISC-V 32-bit pipelined core (Minerva by Lambdaconcept).
* 100MHz clock frequency.
* Runs a Rust "hello world" program.
Use nixpkgs unstable (known to work with ae71c13). Check https://nixbld.m-labs.hk/project/fpga for the status of the build with other nixpkgs versions. Use nixpkgs unstable (known to work with ae71c13). Check https://nixbld.m-labs.hk/project/fpga for the status of the build with other nixpkgs versions.