From 87b4b357c32d3cb607a750008230048753a772cb Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 24 Jun 2019 18:25:44 +0800
Subject: [PATCH] README: add some details

---
 README.md | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index e3882fd..4313297 100644
--- a/README.md
+++ b/README.md
@@ -8,7 +8,11 @@ This is work in progress!
 "Hello World" SoC demo
 ----------------------
 
-Softcore RISC-V system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain. Runs a Rust "hello world" program.
+Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain.
+
+* RISC-V 32-bit pipelined core (Minerva by Lambdaconcept).
+* 100MHz clock frequency.
+* Runs a Rust "hello world" program.
 
 Use nixpkgs unstable (known to work with ae71c13). Check https://nixbld.m-labs.hk/project/fpga for the status of the build with other nixpkgs versions.