M-Labs/HeavyX
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firmware: simulable demo

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Run:
qemu-system-riscv32 -nographic -machine sifive_u -kernel target/riscv32imc-unknown-none-elf/release/helloworld
This commit is contained in:
Sebastien Bourdeauducq 2019-06-06 10:33:29 +08:00
parent b5ac2e7303
commit 78f67f82d3
2 changed files with 9 additions and 3 deletions
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4
firmware/memory.x
View File

@ -1,5 +1,5 @@
MEMORY
{
FLASH : ORIGIN = 0x20000000, LENGTH = 16M
RAM : ORIGIN = 0x80000000, LENGTH = 16K
FLASH : ORIGIN = 0x80000000, LENGTH = 16M
RAM : ORIGIN = 0x81000000, LENGTH = 16K
}

8
firmware/src/main.rs
View File

@ -8,5 +8,11 @@ use riscv_rt::entry;
#[entry]
fn main() -> ! {
loop {}
let foo = "hello world\n";
loop {
for c in foo.chars() {
let mem = 0x1001_3000 as *mut u8;
unsafe { *mem = c as u8 }
}
}
}