add VexRiscv

pull/1/head
Sebastien Bourdeauducq 2019-04-05 18:58:11 +08:00
parent 584dba9ed0
commit 1bf9b5eb2b
3 changed files with 34 additions and 0 deletions

28
cores/vexriscv.nix Normal file
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@ -0,0 +1,28 @@
{ runCommand, fetchFromGitHub, makeWrapper, scala-spinalhdl, name, scalaToRun }:
let
vexriscv-src = fetchFromGitHub {
rev = "d63c6818df8c7229ee9c2ffa83181748b930e1d9";
owner = "SpinalHDL";
repo = "VexRiscv";
sha256 = "1q707icib7q7x9njm4f73g36jjs9q1cvfpv10w6a4jhswg63zyga";
};
vexriscv-compiled = runCommand "vexriscv-compiled" {}
''
mkdir $out
${scala-spinalhdl}/bin/scalac-spinalhdl -d $out/VexRiscv.jar `find ${vexriscv-src}/src/main/scala -type f`
'';
scala-vexriscv = runCommand "scala-vexriscv" { nativeBuildInputs = [ makeWrapper ]; }
''
mkdir -p $out/bin
makeWrapper ${scala-spinalhdl}/bin/scala-spinalhdl $out/bin/scala-vexriscv --prefix CLASSPATH : ${vexriscv-compiled}/VexRiscv.jar
'';
in
runCommand name {}
''
mkdir $out
cd $out
${scala-vexriscv}/bin/scala-vexriscv ${scalaToRun}
mkdir -p $out/nix-support
echo file verilog $out/VexRiscv.v >> $out/nix-support/hydra-build-products
''

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@ -7,6 +7,11 @@ rec {
jtagtap = pkgs.callPackage ./cores/jtagtap.nix { inherit nmigen; };
minerva = pkgs.callPackage ./cores/minerva.nix { inherit nmigen; inherit jtagtap; };
vexriscv-small = pkgs.callPackage ./cores/vexriscv.nix {
inherit scala-spinalhdl;
name = "vexriscv-small";
scalaToRun = "vexriscv.demo.GenSmallAndProductive";
};
heavycomps = pkgs.callPackage ./heavycomps.nix { inherit nmigen; };

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@ -33,4 +33,5 @@ in
''
mkdir -p $out/bin
makeWrapper ${scala_2_11}/bin/scala $out/bin/scala-spinalhdl --prefix CLASSPATH : ${fmtJars}
makeWrapper ${scala_2_11}/bin/scalac $out/bin/scalac-spinalhdl --prefix CLASSPATH : ${fmtJars}
''