Next-generation FPGA SoC toolkit
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  1. { stdenv, fetchFromGitHub, python3Packages, nmigen, jtagtap,
  2. yosys, symbiyosys, yices }:
  3. python3Packages.buildPythonPackage {
  4. name = "minerva";
  5. src = fetchFromGitHub {
  6. owner = "lambdaconcept";
  7. repo = "minerva";
  8. rev = "0518621134dd7a551cac5758d9171a24d0c1578f";
  9. sha256 = "1iqddkfmki7wsb3nsrp145d8qfjv3i9fpgkzvh95rq9nz4l7jy6w";
  10. };
  11. propagatedBuildInputs = [ nmigen jtagtap ];
  12. checkInputs = [ yosys symbiyosys yices ];
  13. checkPhase = "python -m unittest discover minerva.test -v";
  14. meta = with stdenv.lib; {
  15. description = "A 32-bit RISC-V soft processor";
  16. homepage = "https://m-labs.hk/migen";
  17. license = licenses.bsd2;
  18. maintainers = [ maintainers.sb0 ];
  19. };
  20. }