Next-generation FPGA SoC toolkit
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{ stdenv, fetchFromGitHub, python3Packages, nmigen, jtagtap,
yosys, symbiyosys, yices }:
python3Packages.buildPythonPackage {
name = "minerva";
src = fetchFromGitHub {
owner = "lambdaconcept";
repo = "minerva";
rev = "0518621134dd7a551cac5758d9171a24d0c1578f";
sha256 = "1iqddkfmki7wsb3nsrp145d8qfjv3i9fpgkzvh95rq9nz4l7jy6w";
};
propagatedBuildInputs = [ nmigen jtagtap ];
checkInputs = [ yosys symbiyosys yices ];
checkPhase = "python -m unittest discover minerva.test -v";
meta = with stdenv.lib; {
description = "A 32-bit RISC-V soft processor";
homepage = "https://m-labs.hk/migen";
license = licenses.bsd2;
maintainers = [ maintainers.sb0 ];
};
}