HeavyX/examples/helloworld_kintex7.py

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from nmigen import *
from nmigen.back import verilog
from heavycomps import uart
class Top:
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def __init__(self, baudrate=115200):
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self.baudrate = baudrate
self.clk156_p = Signal()
self.clk156_n = Signal()
self.serial_tx = Signal()
def elaborate(self, platform):
m = Module()
cd_sync = ClockDomain(reset_less=True)
m.domains += cd_sync
m.submodules.clock = Instance("IBUFGDS",
i_I=self.clk156_p, i_IB=self.clk156_n, o_O=cd_sync.clk)
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string = "Hello World!\r\n"
mem = Memory(width=8, depth=len(string),
init=[ord(c) for c in string])
m.submodules.rdport = rdport = mem.read_port(synchronous=False)
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tx = uart.RS232TX(round(2**32*self.baudrate/156e6))
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m.submodules.tx = tx
m.d.comb += [
tx.stb.eq(1),
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tx.data.eq(rdport.data),
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self.serial_tx.eq(tx.tx)
]
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with m.If(tx.ack):
with m.If(rdport.addr == len(string) - 1):
m.d.sync += rdport.addr.eq(0)
with m.Else():
m.d.sync += rdport.addr.eq(rdport.addr + 1)
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return m
def main():
top = Top()
output = verilog.convert(Fragment.get(top, None),
ports=(top.clk156_p, top.clk156_n, top.serial_tx))
print(output)
if __name__ == "__main__":
main()