130 lines
4.5 KiB
Rust
130 lines
4.5 KiB
Rust
#![no_std]
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#![no_main]
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extern crate panic_itm;
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use cortex_m::{iprint, iprintln};
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use cortex_m_rt::entry;
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use embedded_hal::watchdog::{WatchdogEnable, Watchdog};
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::delay::DelayMs;
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use stm32f4xx_hal::{
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rcc::RccExt,
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gpio::GpioExt,
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watchdog::IndependentWatchdog,
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time::U32Ext,
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stm32::{CorePeripherals, Peripherals},
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delay::Delay,
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spi::Spi
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};
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use enc424j600;
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use enc424j600::EthController;
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#[entry]
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fn main() -> ! {
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let mut cp = CorePeripherals::take().unwrap();
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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let dp = Peripherals::take().unwrap();
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let clocks = dp.RCC.constrain()
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.cfgr
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.sysclk(168.mhz())
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.hclk(168.mhz())
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.pclk1(32.mhz())
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.pclk2(64.mhz())
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.freeze();
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let mut delay = Delay::new(cp.SYST, clocks);
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let mut itm = cp.ITM;
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let stim0 = &mut itm.stim[0];
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iprintln!(stim0,
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"Eth TX Pinging on STM32-H407 via NIC100/ENC424J600");
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// NIC100 / ENC424J600 Set-up
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let spi1 = dp.SPI1;
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let gpioa = dp.GPIOA.split();
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// Mapping: see Table 9, STM32F407ZG Manual
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let spi1_sck = gpioa.pa5.into_alternate_af5();
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let spi1_miso = gpioa.pa6.into_alternate_af5();
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let spi1_mosi = gpioa.pa7.into_alternate_af5();
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let spi1_nss = gpioa.pa4.into_push_pull_output();
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// Map SPISEL: see Table 1, NIC100 Manual
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let mut spisel = gpioa.pa1.into_push_pull_output();
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spisel.set_high().unwrap();
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delay.delay_ms(1_u32);
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spisel.set_low().unwrap();
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// Create SPI1 for HAL
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::SPI_MODE, enc424j600::spi::SPI_CLOCK.into(),
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clocks);
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let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
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// Init
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match spi_eth.init_dev() {
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Ok(_) => {
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iprintln!(stim0, "Ethernet initialised.")
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}
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Err(_) => {
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panic!("Ethernet initialisation Failed!")
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}
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}
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delay.delay_ms(1_u32);
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iprintln!(stim0,
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"- Delayed 1000us (>=256us), PHY regs are now available");
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// Read MAC
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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spi_eth.read_from_mac(&mut eth_mac_addr);
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iprintln!(stim0,
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"MAC Address = {:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x}",
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eth_mac_addr[5], eth_mac_addr[4],
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eth_mac_addr[3], eth_mac_addr[2],
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eth_mac_addr[1], eth_mac_addr[0]);
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// Set to promiscuous mode
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spi_eth.set_promiscuous();
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iprintln!(stim0,
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"Promiscuous Mode ON");
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// Init Rx/Tx buffers
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spi_eth.init_rxbuf();
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spi_eth.init_txbuf();
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// Testing Eth TX
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let eth_tx_dat: [u8; 64] = [
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60,
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0x6e, 0x44, 0x42, 0x95, 0x08, 0x06, 0x00, 0x01,
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0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60,
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0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8,
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0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
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];
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loop {
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let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
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eth_tx_packet.update_frame(ð_tx_dat, 64);
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iprintln!(stim0,
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"Sending packet (len={:}): \
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dest={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
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src={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
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data={:02x}{:02x}{:02x}{:02x} {:02x}{:02x}{:02x}{:02x} ...",
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eth_tx_packet.get_frame_length(),
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eth_tx_packet.get_frame_byte(0), eth_tx_packet.get_frame_byte(1), eth_tx_packet.get_frame_byte(2),
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eth_tx_packet.get_frame_byte(3), eth_tx_packet.get_frame_byte(4), eth_tx_packet.get_frame_byte(5),
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eth_tx_packet.get_frame_byte(6), eth_tx_packet.get_frame_byte(7), eth_tx_packet.get_frame_byte(8),
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eth_tx_packet.get_frame_byte(9), eth_tx_packet.get_frame_byte(10), eth_tx_packet.get_frame_byte(11),
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eth_tx_packet.get_frame_byte(12), eth_tx_packet.get_frame_byte(13),
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eth_tx_packet.get_frame_byte(14), eth_tx_packet.get_frame_byte(15),
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eth_tx_packet.get_frame_byte(16), eth_tx_packet.get_frame_byte(17),
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eth_tx_packet.get_frame_byte(18), eth_tx_packet.get_frame_byte(19)
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);
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spi_eth.send_raw_packet(eth_tx_packet);
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iprintln!(stim0,
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"Packet sent");
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delay.delay_ms(100_u32);
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}
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unreachable!()
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}
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