renet
/
ENC424J600
10
1
Fork 1
Code Issues 3 Pull Requests 1 Projects Releases Wiki Activity

Rename functions & classes for clarity 

* EthController → EthPhy
  * ::receive_next() → ::recv_packet()
  * ::send_raw_packet() → ::send_packet()
* SpiEth -> Enc424j600
  * ::read_from_mac() → ::read_mac_addr()
  * ::write_mac_address() → ::write_mac_addr()
* EthControllerError → Error
  * ::GeneralError → ::RegisterError
* spi::SpiPortError -> spi::Error
fix-spi
Harry Ho 2021-04-29 17:07:28 +08:00
parent 3529fcd192
commit b9b28f0725
4 changed files with 58 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
src/lib.rs
View File

@ -21,30 +21,30 @@ pub mod nal;
pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
/// Trait representing PHY layer of ENC424J600
pub trait EthController {
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
pub trait EthPhy {
fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error>;
fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error>;
}
/// TODO: Improve these error types
#[derive(Debug)]
pub enum EthControllerError {
pub enum Error {
SpiPortError,
GeneralError,
RegisterError,
// TODO: Better name?
NoRxPacketError
}
impl From<spi::SpiPortError> for EthControllerError {
fn from(_: spi::SpiPortError) -> EthControllerError {
EthControllerError::SpiPortError
impl From<spi::Error> for Error {
fn from(_: spi::Error) -> Error {
Error::SpiPortError
}
}
/// Ethernet controller using SPI interface
pub struct SpiEth<SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> {
/// ENC424J600 controller in SPI mode
pub struct Enc424j600<SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> {
spi_port: spi::SpiPort<SPI, NSS, F>,
rx_buf: rx::RxBuffer,
tx_buf: tx::TxBuffer
@ -52,22 +52,22 @@ pub struct SpiEth<SPI: Transfer<u8>,
impl <SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> SpiEth<SPI, NSS, F> {
F: FnMut(u32) -> ()> Enc424j600<SPI, NSS, F> {
pub fn new(spi: SPI, nss: NSS, delay_ns: F) -> Self {
SpiEth {
Enc424j600 {
spi_port: spi::SpiPort::new(spi, nss, delay_ns),
rx_buf: rx::RxBuffer::new(),
tx_buf: tx::TxBuffer::new()
}
}
pub fn init_dev(&mut self) -> Result<(), EthControllerError> {
pub fn reset(&mut self) -> Result<(), Error> {
// Write 0x1234 to EUDAST
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
// Verify that EUDAST is 0x1234
let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x1234 {
return Err(EthControllerError::GeneralError)
return Err(Error::RegisterError)
}
// Poll CLKRDY (ESTAT<12>) to check if it is set
loop {
@ -81,13 +81,13 @@ impl <SPI: Transfer<u8>,
// Verify that EUDAST is 0x0000
eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x0000 {
return Err(EthControllerError::GeneralError)
return Err(Error::RegisterError)
}
self.spi_port.delay_us(256);
Ok(())
}
pub fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
pub fn init_rxbuf(&mut self) -> Result<(), Error> {
// Set ERXST pointer
self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
// Set ERXTAIL pointer
@ -100,14 +100,14 @@ impl <SPI: Transfer<u8>,
Ok(())
}
pub fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
pub fn init_txbuf(&mut self) -> Result<(), Error> {
// Set EGPWRPT pointer
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
Ok(())
}
/// Set controller to Promiscuous Mode
pub fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
pub fn set_promiscuous(&mut self) -> Result<(), Error> {
// From Section 10.12, ENC424J600 Data Sheet:
// "To accept all incoming frames regardless of content (Promiscuous mode),
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
@ -117,7 +117,7 @@ impl <SPI: Transfer<u8>,
}
/// Read MAC to [u8; 6]
pub fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
pub fn read_mac_addr(&mut self, mac: &mut [u8]) -> Result<(), Error> {
mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
@ -127,7 +127,7 @@ impl <SPI: Transfer<u8>,
Ok(())
}
pub fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError> {
pub fn write_mac_addr(&mut self, mac: &[u8]) -> Result<(), Error> {
self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
@ -140,17 +140,17 @@ impl <SPI: Transfer<u8>,
impl <SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> EthController for SpiEth<SPI, NSS, F> {
F: FnMut(u32) -> ()> EthPhy for Enc424j600<SPI, NSS, F> {
/// Receive the next packet and return it
/// Set is_poll to true for returning until PKTIF is set;
/// Set is_poll to false for returning Err when PKTIF is not set
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error> {
// Poll PKTIF (EIR<4>) to check if it is set
loop {
let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
if eir & 0x40 == 0x40 { break }
if !is_poll {
return Err(EthControllerError::NoRxPacketError)
return Err(Error::NoRxPacketError)
}
}
// Set ERXRDPT pointer to next_addr
@ -186,7 +186,7 @@ impl <SPI: Transfer<u8>,
}
/// Send an established packet
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError> {
fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error> {
// Set EGPWRPT pointer to next_addr
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
// Copy packet data to SRAM Buffer

2
src/nal.rs
View File

@ -24,7 +24,7 @@ pub enum NetworkError {
pub type NetworkInterface<SPI, NSS> = net::iface::EthernetInterface<
'static,
crate::smoltcp_phy::SmoltcpDevice<
crate::SpiEth<SPI, NSS, fn(u32)>
crate::Enc424j600<SPI, NSS, fn(u32)>
>,
>;

34
src/smoltcp_phy.rs
View File

@ -1,5 +1,5 @@
use crate::{
EthController, tx, RAW_FRAME_LENGTH_MAX
EthPhy, tx, RAW_FRAME_LENGTH_MAX
};
use core::cell;
use smoltcp::{
@ -8,25 +8,25 @@ use smoltcp::{
Error
};
pub struct SmoltcpDevice<EC: EthController> {
pub eth_controller: cell::RefCell<EC>,
pub struct SmoltcpDevice<E: EthPhy> {
pub eth_phy: cell::RefCell<E>,
rx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX]
}
impl<EC: EthController> SmoltcpDevice<EC> {
pub fn new(eth_controller: EC) -> Self {
impl<E: EthPhy> SmoltcpDevice<E> {
pub fn new(eth_phy: E) -> Self {
SmoltcpDevice {
eth_controller: cell::RefCell::new(eth_controller),
eth_phy: cell::RefCell::new(eth_phy),
rx_packet_buf: [0; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [0; RAW_FRAME_LENGTH_MAX]
}
}
}
impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
impl<'a, E: 'a + EthPhy> Device<'a> for SmoltcpDevice<E> {
type RxToken = EthRxToken<'a>;
type TxToken = EthTxToken<'a, EC>;
type TxToken = EthTxToken<'a, E>;
fn capabilities(&self) -> DeviceCapabilities {
let mut caps = DeviceCapabilities::default();
@ -35,8 +35,8 @@ impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
}
fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
match self.eth_controller.borrow_mut().receive_next(false) {
let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
match self.eth_phy.borrow_mut().recv_packet(false) {
Ok(rx_packet) => {
// Write received packet to RX packet buffer
rx_packet.write_frame_to(&mut self.rx_packet_buf);
@ -57,7 +57,7 @@ impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
}
fn transmit(&'a mut self) -> Option<Self::TxToken> {
let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
// Construct a blank TxToken
let tx_token = EthTxToken {
buf: &mut self.tx_packet_buf,
@ -81,12 +81,12 @@ impl<'a> RxToken for EthRxToken<'a> {
}
}
pub struct EthTxToken<'a, EC: EthController> {
pub struct EthTxToken<'a, E: EthPhy> {
buf: &'a mut [u8],
dev: *mut SmoltcpDevice<EC>
dev: *mut SmoltcpDevice<E>
}
impl<'a, EC: 'a + EthController> TxToken for EthTxToken<'a, EC> {
impl<'a, E: 'a + EthPhy> TxToken for EthTxToken<'a, E> {
fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R, Error>
where
F: FnOnce(&mut [u8]) -> Result<R, Error>,
@ -97,10 +97,10 @@ impl<'a, EC: 'a + EthController> TxToken for EthTxToken<'a, EC> {
// Update frame length and write frame bytes
tx_packet.update_frame(&mut self.buf[..len], len);
// Send the packet as raw
let eth_controller = unsafe {
&mut (*self.dev).eth_controller
let eth_phy = unsafe {
&mut (*self.dev).eth_phy
};
match eth_controller.borrow_mut().send_raw_packet(&tx_packet) {
match eth_phy.borrow_mut().send_packet(&tx_packet) {
Ok(_) => { result },
Err(_) => Err(Error::Exhausted)
}

28
src/spi.rs
View File

@ -59,7 +59,7 @@ pub struct SpiPort<SPI: Transfer<u8>,
delay_ns: F,
}
pub enum SpiPortError {
pub enum Error {
TransferError
}
@ -78,13 +78,13 @@ impl <SPI: Transfer<u8>,
}
}
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, Error> {
// Using RCRU instruction to read using unbanked (full) address
let r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
Ok(r_data)
}
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SpiPortError> {
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, Error> {
let r_data_lo = self.read_reg_8b(lo_addr)?;
let r_data_hi = self.read_reg_8b(lo_addr + 1)?;
// Combine top and bottom 8-bit to return 16-bit
@ -93,7 +93,7 @@ impl <SPI: Transfer<u8>,
// Currently requires manual slicing (buf[1..]) for the data read back
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-> Result<(), SpiPortError> {
-> Result<(), Error> {
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
Ok(r_valid)
}
@ -101,19 +101,19 @@ impl <SPI: Transfer<u8>,
// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
// TODO: Maybe better naming?
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-> Result<(), SpiPortError> {
-> Result<(), Error> {
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
Ok(w_valid)
}
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), SpiPortError> {
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), Error> {
// TODO: addr should be separated from w_data
// Using WCRU instruction to write using unbanked (full) address
self.rw_addr_u8(opcodes::WCRU, addr, data)?;
Ok(())
}
pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), SpiPortError> {
pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), Error> {
self.write_reg_8b(lo_addr, (data & 0xff) as u8)?;
self.write_reg_8b(lo_addr + 1, ((data & 0xff00) >> 8) as u8)?;
Ok(())
@ -127,7 +127,7 @@ impl <SPI: Transfer<u8>,
// TODO: (Make data read/write as reference to array)
// Currently requires 1-byte addr, read/write data is only 1-byte
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
-> Result<u8, SpiPortError> {
-> Result<u8, Error> {
// Enable chip select
self.nss.set_low();
// Start writing to SLAVE
@ -150,7 +150,7 @@ impl <SPI: Transfer<u8>,
(self.delay_ns)(60);
self.nss.set_high();
(self.delay_ns)(30);
Err(SpiPortError::TransferError)
Err(Error::TransferError)
}
}
}
@ -161,7 +161,7 @@ impl <SPI: Transfer<u8>,
// Note: buf must be at least (data_length + 1)-byte long
// TODO: Check and raise error for array size < (data_length + 1)
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-> Result<(), SpiPortError> {
-> Result<(), Error> {
// Enable chip select
self.nss.set_low();
// Start writing to SLAVE
@ -176,7 +176,7 @@ impl <SPI: Transfer<u8>,
Err(_) => {
// Disable chip select
self.nss.set_high();
Err(SpiPortError::TransferError)
Err(Error::TransferError)
}
}
}
@ -184,7 +184,7 @@ impl <SPI: Transfer<u8>,
// Note: buf[0] is currently reserved for opcode to overwrite
// TODO: Actual data should start from buf[0], not buf[1]
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-> Result<(), SpiPortError> {
-> Result<(), Error> {
// Enable chip select
self.nss.set_low();
// Start writing to SLAVE
@ -200,8 +200,8 @@ impl <SPI: Transfer<u8>,
Err(_) => {
// Disable chip select
self.nss.set_high();
Err(SpiPortError::TransferError)
Err(Error::TransferError)
}
}
}
}
}