Commit Graph

1411 Commits

Author SHA1 Message Date
279376a373 standalone: Emit IRRT IR 2023-09-30 09:31:18 +08:00
b6afd1bfda standalone: Split check_demos into check_demo
Allows individual tests to be executed.
2023-09-30 09:31:18 +08:00
be3e8f50a2 standalone: Refactor demo library to C
Needed for use by lli.
2023-09-30 09:31:18 +08:00
059d3da58b standalone: Add float64 output tests 2023-09-30 09:31:18 +08:00
9b28f23d8c flake: Add clang alongside clang-unwrapped 2023-09-30 09:31:18 +08:00
119f4d63e9 cargo: update dependencies 2023-09-29 14:46:22 +08:00
458fa12788 flake: update dependencies 2023-09-29 14:07:47 +08:00
48c6498d1f core: Fix restoration of loop target in try statement
old_loop_target is only assigned if ctx.loop_target is overwritten,
meaning that if ctx.loop_target is never overwritten, ctx.loop_target
will always be overwritten to None.

We fix this by only restoring from old_loop_target if we previously
assigned to old_loop_target.
2023-09-28 20:00:02 +08:00
2a38d5160e meta: Respect opt flags when performing whole-module optimization 2023-09-28 19:58:54 +08:00
b39831b388 standalone: Update demos
- Add `output_str` for printing a string
- Add demo_test.py to test interop
2023-09-28 19:58:53 +08:00
cb39f61e79 core: Fix passing structure arguments to extern functions
All parameters with a structure type in extern functions are marked as
`byref` instead of `byval`, as most ABIs require the first several
arguments to be passed in registers before spilling into the stack.

`byval` breaks this contract by explicitly requiring all arguments to be
 passed in the stack, breaking interop with libraries written in other
 languages.
2023-09-28 15:02:35 +08:00
176f250bdb core: Fix missing conversion to i1 for IfExp 2023-09-28 10:06:40 +08:00
acdb1de6fe meta: Improve documentation for various modified classes 2023-09-25 15:42:07 +08:00
31dcd2dde9 core: Use i8 for boolean variable allocation
In LLVM, i1 represents a 1-byte integer with a single valid bit; The
rest of the 7 upper bits are undefined. This causes problems when
using these variables in memory operations (e.g. memcpy/memmove as
needed by List slicing and assignment).

We fix this by treating all local boolean variables as i8 so that they
are well-defined for memory operations. Function ABIs will continue to
use i1, as memory operations cannot be directly performed on function
arguments or return types, instead they are always converted back into
local boolean variables (which are i8s anyways).

Fixes #315.
2023-09-25 15:42:07 +08:00
fc93fc2f0e core: Move bitcode verification error message into panic message 2023-09-22 17:16:29 +08:00
dd42022633 core: Minor refactor allocate_list 2023-09-22 17:16:29 +08:00
6dfc43c8b0 core: Add name to build_gep_and_load 2023-09-22 17:16:29 +08:00
ab2360d7a0 core: Remove emit_llvm from CodeGenLLVMOptions
We instead output an LLVM bitcode file when the option is specified on
the command-line.
2023-09-22 17:16:29 +08:00
ee1ee4ab3b core: Replace deprecated _ExtInt with _BitInt 2023-09-22 17:16:29 +08:00
3e430b9b40 core: Fix missing changes for codegen tests
Apparently the changes were dropped after rebasing.
2023-09-22 17:16:21 +08:00
9e57498958 meta: Update dependencies 2023-09-21 09:38:38 +08:00
769fd01df8 meta: Allow specifying compiler arguments for check_demos 2023-09-18 11:35:20 +08:00
411837cacd artiq: Specify target CPU when creating LLVM target options
We can try to optimize for the host and Cortex-A9 chips; The RISC-V
ISAs do not target specific chips, so we will fallback to using the
generic CPU.
2023-09-18 11:35:20 +08:00
f59d45805f standalone: Add command line flags for target properties
For testing codegen for different platforms on the host system.
2023-09-18 11:35:20 +08:00
048fcb0a69 core: Switch to LLVM New Pass Manager 2023-09-18 11:35:15 +08:00
676d07657a core: Add target field to CodeGenLLVMOptions
For specifying the target machine options when optimizing and linking.

This field is currently unused but will be required in a future
commit.
2023-09-18 09:46:24 +08:00
2482a1ef9b core: Add CodeGenTargetMachineOptions
Needed in a future commit.
2023-09-18 09:41:49 +08:00
eb63f2ad48 meta: Update to Rust Edition 2021 2023-09-15 10:25:50 +08:00
ff27e22ee6 flake: switch back to nixpkgs unstable
Too many issues with python-updates branch for now.
2023-09-13 19:15:47 +08:00
d672ef094b msys2: update packages, Python 3.11 2023-09-13 09:50:33 +08:00
d25921230e switch to Python 3.11 2023-09-13 09:44:08 +08:00
66f07b5bf4 flake: switch to nixos-unstable 2023-09-12 18:14:39 +08:00
008d50995c meta: Update run_demo.sh
- Allow more than one argument to nac3standalone executable
2023-09-12 16:20:50 +08:00
474f9050ce standalone: Expose flags in command-line 2023-09-12 16:20:49 +08:00
3993a5cf3f core: Add LLVM options to WorkerRegistry 2023-09-12 10:57:05 +08:00
39724de598 core: Add CodeGenLLVMOptions
For specifying LLVM options during code generation.
2023-09-12 10:57:04 +08:00
e4940247f3 standalone: Implement command-line parser using clap
In preparation for adding more command-line options.
2023-09-12 10:08:34 +08:00
4481d48709 core: Use C-style for loop logic for iterables
Index increment is now performed at the end of the loop body.
2023-09-06 20:09:38 +08:00
b4983526bd core: Remove redundant for.cond BB for iterable loops
Simplifies logic for creating basic blocks.
2023-09-06 20:09:37 +08:00
b4a9616648 core: Add assertion for when range has step of 0
Aligns with the behavior in Python.
2023-09-06 20:09:36 +08:00
e0de82993f core: Preserve value of variable shadowed by for loop
Previously, the final value of the target expression would be one after
the last element of the loop, which does not match Python's behavior.

This commit fixes this problem while also preserving the last assigned
value of the loop beyond the loop, matching Python's behavior.
2023-09-06 20:09:36 +08:00
6805253515 core: Use AST var name for IR name
Aids debugging IR.
2023-09-06 20:09:36 +08:00
19915bac79 core: Prepend statement type to basic block label names
Aids debugging IR.
2023-09-06 20:09:36 +08:00
17b4686260 standalone: Adapt loop example to output loop variable 2023-09-06 18:56:45 +08:00
6de0884dc1 core: Use anonymous name for variables if unspecified
The current default prefix is only derived from the instruction type,
which is not helpful during the comprehension of the IR. Changing to
anonymous names (e.g. %1) helps understand that the variable is only
needed as part of a larger (possibly named) expression.
2023-09-06 14:02:15 +08:00
f1b0e05b3d core: Rename IR variables
Because it is unclear which variables are expressions and
subexpressions, all variables which are previously anonymous are named
using (1) the control flow statement if available, (2) the possible name
of the variable as inferred from the variable name in Rust, and (3) the
"addr" prefix to indicate that the values are pointers. These three
strings are joint together using '.', forming "for.i.addr" for instance.
2023-09-06 14:02:15 +08:00
ff23968544 core: Add name parameter to gen_{var_alloc,store_target}
This allows variables in the IR to be assigned a custom name as opposed
to names with a default prefix.
2023-09-06 11:00:02 +08:00
049908044a flake: update dependencies 2023-09-04 11:00:15 +08:00
d37287a33d Cargo: Update dependencies 2023-09-04 10:43:57 +08:00
283bd7c69a cargo: update dependencies 2023-07-14 10:57:21 +08:00