ychenfo
/
nac3
forked from M-Labs/nac3
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

nac3embedded: switch to Zynq (#24)

This commit is contained in:
Sebastien Bourdeauducq 2021-09-24 14:45:01 +08:00
parent 4535b60fc0
commit 7ab2114882
2 changed files with 13 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
nac3embedded/device_db.py
View File

@ -1,13 +1,16 @@
# python demo.py
# artiq_run module.elf
core_addr = "192.168.1.50"
device_db = {
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1e-9}
}
"arguments": {
"host": "192.168.1.52",
"ref_period": 1e-9,
"ref_multiplier": 8,
"target": "cortexa9"
}
},
}

8
nac3embedded/src/lib.rs
View File

@ -147,14 +147,18 @@ impl Nac3 {
builder.populate_module_pass_manager(&passes);
passes.run_on(module);
let triple = TargetTriple::create("riscv32-unknown-linux");
// For RISC-V (needs https://git.m-labs.hk/M-Labs/nac3/issues/24)
//let triple = TargetTriple::create("riscv32-unknown-linux");
//let features = "+a,+m";
let triple = TargetTriple::create("armv7-unknown-linux-gnueabihf");
let features = "+dsp,+fp16,+neon,+vfp3";
let target =
Target::from_triple(&triple).expect("couldn't create target from target triple");
let target_machine = target
.create_target_machine(
&triple,
"",
"+a,+m",
features,
OptimizationLevel::Default,
RelocMode::PIC,
CodeModel::Default,