Sebastien Bourdeauducq
|
68045ce0c5
|
mark RTIO clock as asychronous to system clock
|
2020-07-08 20:37:53 +08:00 |
Sebastien Bourdeauducq
|
7ee67db8e3
|
use IOSERDES TTL
|
2020-07-08 20:02:46 +08:00 |
Sebastien Bourdeauducq
|
bd7d58e239
|
add RTIO PLL and clock source selection
|
2020-07-08 19:58:13 +08:00 |
Sebastien Bourdeauducq
|
b13da96835
|
increase CSR bus width to 32 bits
Before:
Minimum interval for sustained TTL output switching ... 1.554e-06
After:
Minimum interval for sustained TTL output switching ... 5.17e-07
|
2020-07-07 17:22:07 +08:00 |
Sebastien Bourdeauducq
|
1222db56e1
|
use different user_led to avoid VADJ problems with NIST backplanes
|
2020-05-14 09:23:43 +08:00 |
Sebastien Bourdeauducq
|
b2fe33f6ea
|
zc706: add support for NIST backplanes
|
2020-05-07 17:05:00 +08:00 |
Sebastien Bourdeauducq
|
4464b85ab3
|
move build artifacts out of tree
|
2020-05-07 13:52:40 +08:00 |
Sebastien Bourdeauducq
|
2439ba1f88
|
add impure incremental build process, document
|
2020-05-01 10:07:38 +08:00 |