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artiq-zynq
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Code Pull Requests Activity
351 Commits 3 Branches 0 Tags 1.8 MiB
Commit Graph

53 Commits

Author SHA1 Message Date
Astro bb35d6b46a default.nix: update cargosha256 2020-08-17 19:21:25 +02:00
Sebastien Bourdeauducq 3a8a025d5f update dependencies, zc706 -> zynq-rs 2020-08-06 20:33:23 +08:00
pca006132 e7752a3d6d runtime/kernel: fixes core0 memory leak. 
Fixes #85
 2020-08-06 09:39:49 +08:00
pca006132 a9c40f7478 Updated cargoSha256. 2020-08-04 14:40:02 +08:00
Sebastien Bourdeauducq a5938b0fd6 default.nix: add ACPKI-enabled builds 2020-08-04 13:17:33 +08:00
pca006132 7f4ccc9ded Updated cargoSha256 2020-08-04 10:47:52 +08:00
Sebastien Bourdeauducq 673ad3fd8e update cargosha256 2020-07-25 12:22:31 +08:00
Astro 845f98242b update cargosha256 2020-07-23 01:06:50 +02:00
Sebastien Bourdeauducq e0560a2db9 expose libm functions to kernel 2020-07-21 13:50:33 +08:00
Sebastien Bourdeauducq 367d54293b update cargosha256 2020-07-19 16:47:49 +08:00
pca006132 92405ffe91 logger: changed from RefCell to Mutex. 2020-07-15 17:04:16 +08:00
pca006132 62f39e2c08 mgmt: Implemented network log access. 2020-07-13 15:15:06 +08:00
Sebastien Bourdeauducq f1f7fe8da6 fix gateware pure build 2020-07-13 10:44:25 +08:00
Sebastien Bourdeauducq e3ff21b1b5 create gateware folder 2020-07-11 17:49:54 +08:00
Sebastien Bourdeauducq 67ff3c36e2 drop FSBL 
All SZL and Zynq startup issues seem resolved.
 2020-07-07 19:44:14 +08:00
Sebastien Bourdeauducq a8de572014 set up PL clocks 2020-07-07 19:40:32 +08:00
Sebastien Bourdeauducq e6cf3e90d3 update zc706 2020-07-07 12:50:05 +08:00
Sebastien Bourdeauducq de2c2af523 use new exception vectors 2020-07-06 21:16:32 +08:00
Sebastien Bourdeauducq bbc1ffec8e szl: disable ps7_init 2020-07-06 12:31:13 +08:00
Sebastien Bourdeauducq bbe6812792 add network address config code 2020-07-06 12:04:22 +08:00
Sebastien Bourdeauducq 2df1a647df update cargosha256 2020-07-06 01:12:23 +08:00
Sebastien Bourdeauducq 3bd4643009 use fpu_enable from zc706 2020-07-06 00:18:28 +08:00
Sebastien Bourdeauducq 6f37128911 use clang-unwrapped 2020-07-02 21:50:19 +08:00
Sebastien Bourdeauducq e6028ec091 update cargosha256 2020-07-02 21:41:35 +08:00
Sebastien Bourdeauducq 8807854b2b fix cargoSha256 2020-07-02 10:31:14 +08:00
Astro d8745074b4 update dependencies 2020-06-27 02:29:45 +02:00
Sebastien Bourdeauducq a71ee143ac update dependencies 2020-06-25 20:21:44 +08:00
Astro f750234cb5 update dependencies 2020-06-18 18:33:32 +02:00
Sebastien Bourdeauducq 854a50a0ba fsbl: clean up buildInputs 2020-06-17 16:23:41 +08:00
pca006132 ec9a70ecc3 FSBL: changed to self-built FSBL (#13) 
Co-authored-by: pca006132 <john.lck40@gmail.com>
 2020-06-17 16:19:59 +08:00
Sebastien Bourdeauducq e43511c95f update dependencies 2020-06-16 18:08:12 +08:00
pca006132 0dc0bb391d
add support for loading bitstream from bootimage. 2020-06-16 17:45:54 +08:00
Sebastien Bourdeauducq f9ccf908dd update dependencies 2020-06-15 17:14:03 +08:00
Sebastien Bourdeauducq dec245e637 default.nix: also use BIF format to contain bitstream for SZL 2020-06-15 17:03:27 +08:00
Sebastien Bourdeauducq dc78868109 update dependencies and add fatfs 2020-06-11 17:36:23 +08:00
Sebastien Bourdeauducq de2618045a update cargoSha256 2020-06-07 22:00:23 +08:00
Sebastien Bourdeauducq 7216e9c4be update cargoSha256 2020-06-05 19:26:50 +08:00
Sebastien Bourdeauducq 15b2b253cf build for NIST variants 2020-05-14 15:30:50 +08:00
Sebastien Bourdeauducq af08b1ad00 update dependencies 2020-05-14 09:28:16 +08:00
Sebastien Bourdeauducq aeefdc862d update dependencies 2020-05-09 13:48:27 +08:00
Sebastien Bourdeauducq 4464b85ab3 move build artifacts out of tree 2020-05-07 13:52:40 +08:00
Sebastien Bourdeauducq 90faeb6fa2 use new core1 startup mechanism 2020-05-06 22:16:34 +08:00
Sebastien Bourdeauducq ae2cee5f7e also work around mkbootimage potential bug with szl 2020-05-06 17:47:27 +08:00
Sebastien Bourdeauducq 27466036a7 work around boot.bin/fsbl problems 
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
 2020-05-06 17:38:01 +08:00
Sebastien Bourdeauducq 7c22b72129 add FSBL startup route 
Not working (Zynq sucks) and not debuggable (can't get UART output from FSBL even with official binaries...)
 2020-05-06 16:53:54 +08:00
Sebastien Bourdeauducq 1211a6d066 build FSBL 2020-05-06 16:02:44 +08:00
Sebastien Bourdeauducq 11d839d8a6 update cargoSha256 2020-05-04 23:02:51 +08:00
Sebastien Bourdeauducq cbd591b86b update dependencies 2020-05-03 09:59:24 +08:00
Astro 9750bb8aa8 default.nix: change <artiq-fast> syntax 2020-05-03 02:25:19 +02:00
Sebastien Bourdeauducq 11b58d801d default.nix: build SD card contents 2020-05-01 11:23:00 +08:00