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add demo build for Kasli-SoC

This commit is contained in:
Sebastien Bourdeauducq 2021-02-15 19:52:13 +08:00
parent c90cb7adad
commit faf9714e10
3 changed files with 8 additions and 7 deletions

View File

@ -8,7 +8,7 @@ let
vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
# FSBL configuration supplied by Vivado 2020.1 for these boards:
fsblTargets = ["zc702" "zc706" "zed"];
build = { target, variant }: let
build = { target, variant, json ? null }: let
szl = (import zynq-rs)."${target}-szl";
fsbl = import "${zynq-rs}/nix/fsbl.nix" {
inherit pkgs;
@ -24,7 +24,7 @@ let
nativeBuildInputs = [
pkgs.gnumake
(pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
(pkgs.python3.withPackages(ps: (with artiqpkgs; [ ps.jsonschema migen migen-axi misoc artiq ])))
cargo-xbuild
pkgs.llvmPackages_9.llvm
pkgs.llvmPackages_9.clang-unwrapped
@ -32,7 +32,7 @@ let
buildPhase = ''
export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
make TARGET=${target} VARIANT=${variant}
make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}"
'';
installPhase = ''
@ -49,12 +49,12 @@ let
gateware = pkgs.runCommand "${target}-${variant}-gateware"
{
nativeBuildInputs = [
(pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
(pkgs.python3.withPackages(ps: (with artiqpkgs; [ ps.jsonschema migen migen-axi misoc artiq ])))
vivado
];
}
''
python ${./src/gateware}/${target}.py -g build -V ${variant}
python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
mkdir -p $out $out/nix-support
cp build/top.bit $out
echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
@ -136,5 +136,6 @@ in
(build { target = "zc706"; variant = "acpki_simple"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
(build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
(build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
{ inherit zynq-rs; }
)

View File

@ -1,5 +1,5 @@
TARGET := zc706
VARIANT := simple
GWARGS := -V simple
all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
@ -8,7 +8,7 @@ all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
../build/pl.rs ../build/rustc-cfg: gateware/*
mkdir -p ../build
python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)
python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg $(GWARGS)
../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -print)
cd runtime && \