svenover
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

satman: wait longer for PLL lock (#246)

This commit is contained in:
Sebastien Bourdeauducq 2023-08-13 13:52:12 +08:00
parent 583b629b40
commit dc08c382a2
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/satman/src/main.rs
View File

@ -633,7 +633,7 @@ pub extern "C" fn main_core0() -> i32 {
unsafe { unsafe {
csr::drtio_transceiver::stable_clkin_write(1); csr::drtio_transceiver::stable_clkin_write(1);
} }
timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock timer.delay_us(50_000); // wait for CPLL/QPLL/MMCM lock
let clk = unsafe { csr::sys_crg::current_clock_read() }; let clk = unsafe { csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");