From 06ad8dfe279a9dc9dbf5ecf50f742967bc587e5f Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Thu, 18 Jun 2020 18:33:47 +0200
Subject: [PATCH] szl: flush now write-buffered dcache of DDR pages before
 executing instructions in them

---
 src/szl/src/main.rs | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs
index d31e074..8b89469 100644
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@@ -7,6 +7,7 @@ use core::mem;
 use log::{info, error};
 use cstr_core::CStr;
 
+use libcortex_a9::cache::dcci_slice;
 use libboard_zynq::{
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
     logger,
@@ -48,6 +49,12 @@ pub fn main_core0() {
     if result < 0 {
         error!("decompression failed");
     } else {
+        // Flush data cache entries for all of DDR, including
+        // Memory/Instruction Symchronization Barriers
+        dcci_slice(unsafe {
+            core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
+        });
+
         // Start core0 only, for compatibility with FSBL.
         info!("executing payload");
         unsafe {