"""Auxiliary controller, common to satellite and master"""

from migen import *
from migen.fhdl.simplify import FullMemoryWE

from misoc.interconnect.csr import *
from migen_axi.interconnect import axi
from artiq.gateware.drtio.aux_controller import Transmitter, Receiver

max_packet = 1024

# TODO: FullMemoryWE should be applied by migen.build
@FullMemoryWE()
class DRTIOAuxController(Module):
    def __init__(self, link_layer):
        self.bus = axi.Interface()
        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.data_width))
        self.submodules.receiver = Receiver(link_layer, len(self.bus.data_width))

        # probably will need to make axi.SDRAM based on wb code
        tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
        rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
        wsb = log2_int(len(self.bus.data_width)//8)
        decoder = axi.AddressDecoder(self.bus,
            [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
             (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
            register=True)
        self.submodules += tx_sdram_if, rx_sdram_if, decoder

    def get_csrs(self):
        return self.transmitter.get_csrs() + self.receiver.get_csrs()