make: change main target names to avoid collision

makefile: target names match target files
added different fw type support for local_run
2021-10-05 11:55:45 +02:00 · 2021-10-05 10:53:58 +02:00 · 2021-10-05 10:04:14 +02:00 · 2021-10-04 12:52:53 +02:00 · 2021-10-04 08:53:38 +02:00 · 2021-10-01 15:37:00 +02:00
40 changed files with 3788 additions and 154 deletions
--- a/default.nix
+++ b/default.nix
@ -8,12 +8,14 @@ let
  vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
  # FSBL configuration supplied by Vivado 2020.1 for these boards:
  fsblTargets = ["zc702" "zc706" "zed"];
+  sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
  build = { target, variant, json ? null }: let
    szl = (import zynq-rs)."${target}-szl";
    fsbl = import "${zynq-rs}/nix/fsbl.nix" {
      inherit pkgs;
      board = target;
    };
+    fwtype = if builtins.elem variant sat_variants then "satman" else "runtime";

    firmware = rustPlatform.buildRustPackage rec {
      # note: due to fetchCargoTarball, cargoSha256 depends on package name
@ -33,15 +35,15 @@ let
        export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
        export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
        export CARGO_HOME=$(mktemp -d cargo-home.XXX)
-        make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}"
+        make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}_target
      '';

      installPhase = ''
        mkdir -p $out $out/nix-support
-        cp ../build/runtime.bin $out/runtime.bin
-        cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
-        echo file binary-dist $out/runtime.bin >> $out/nix-support/hydra-build-products
-        echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
+        cp ../build/${fwtype}.bin $out/${fwtype}.bin
+        cp ../build/firmware/armv7-none-eabihf/release/${fwtype} $out/${fwtype}.elf
+        echo file binary-dist $out/${fwtype}.bin >> $out/nix-support/hydra-build-products
+        echo file binary-dist $out/${fwtype}.elf >> $out/nix-support/hydra-build-products
      '';

      doCheck = false;
@ -66,7 +68,7 @@ let
      ''
        mkdir $out
        ln -s ${szl}/szl.elf $out
-        ln -s ${firmware}/runtime.bin $out
+        ln -s ${firmware}/${fwtype}.bin $out
        ln -s ${gateware}/top.bit $out
      '';
    sd = pkgs.runCommand "${target}-${variant}-sd"
@ -132,11 +134,25 @@ let
 in
  (
    (build { target = "zc706"; variant = "simple"; }) //
+    (build { target = "zc706"; variant = "master"; }) //
+    (build { target = "zc706"; variant = "satellite"; }) //
    (build { target = "zc706"; variant = "nist_clock"; }) //
+    (build { target = "zc706"; variant = "nist_clock_master"; }) //
+    (build { target = "zc706"; variant = "nist_clock_satellite"; }) //
    (build { target = "zc706"; variant = "nist_qc2"; }) //
+    (build { target = "zc706"; variant = "nist_qc2_master"; }) //
+    (build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
    (build { target = "zc706"; variant = "acpki_simple"; }) //
+    (build { target = "zc706"; variant = "acpki_master"; }) //
+    (build { target = "zc706"; variant = "acpki_satellite"; }) //
    (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
    (build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) //
    (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
+    (build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
+    (build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
    { inherit zynq-rs; }
  )
--- a/kasli-soc-master.json
+++ b/kasli-soc-master.json
@ -0,0 +1,60 @@
+{
+    "target": "kasli_soc",
+    "variant": "master",
+    "hw_rev": "v1.0",
+    "base": "master",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}
--- a/kasli-soc-satellite.json
+++ b/kasli-soc-satellite.json
@ -0,0 +1,60 @@
+{
+    "target": "kasli_soc",
+    "variant": "satellite",
+    "hw_rev": "v1.0",
+    "base": "satellite",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}
--- a/local_run.sh
+++ b/local_run.sh
@ -14,8 +14,9 @@ fi
 impure=0
 load_bitstream=1
 board_type="kasli_soc"
+fw_type="runtime"

-while getopts "ilb:t:" opt; do
+while getopts "ilb:t:f:" opt; do
    case "$opt" in
    \?) exit 1
        ;;
@ -27,6 +28,8 @@ while getopts "ilb:t:" opt; do
        ;;
    t)  board_type=$OPTARG
        ;;
+    f)  fw_type=$OPTARG
+        ;;
    esac
 done

@ -49,10 +52,10 @@ if [ $impure -eq 1 ]; then
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g $build_dir/gateware/top.bit"
    fi
-    artiq_netboot $load_bitstream_cmd -f $build_dir/runtime.bin -b $board_host
+    artiq_netboot $load_bitstream_cmd -f $build_dir/$fwtype.bin -b $board_host
 else
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g $result_dir/top.bit"
    fi
-    artiq_netboot $load_bitstream_cmd -f $result_dir/runtime.bin -b $board_host
-fi
+    artiq_netboot $load_bitstream_cmd -f $result_dir/$fwtype.bin -b $board_host
+fi
--- a/remote_run.sh
+++ b/remote_run.sh
@ -20,8 +20,9 @@ impure_dir="build"
 sshopts=""
 load_bitstream=1
 board_host="192.168.1.52"
+fw_type="runtime"

-while getopts "h:id:o:l" opt; do
+while getopts "h:id:o:lt:" opt; do
    case "$opt" in
    \?) exit 1
        ;;
@ -38,6 +39,8 @@ while getopts "h:id:o:l" opt; do
        ;;
    b)  board_host=$OPTARG
        ;;
+    t)  fw_type=$OPTARG
+        ;;
    esac
 done

@ -53,12 +56,12 @@ if [ $impure -eq 1 ]; then
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g build/gateware/top.bit"
    fi
-    firmware="build/runtime.bin"
+    firmware="build/$fw_type.bin"
 else
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g $pure_dir/top.bit"
    fi
-    firmware="$pure_dir/runtime.bin"    
+    firmware="$pure_dir/$fw_type.bin"    
 fi
 echo "Programming board..."
 ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'"
--- a/src/Cargo.toml
+++ b/src/Cargo.toml
@ -3,8 +3,10 @@ members = [
  "libc",
  "libdyld",
  "libdwarf",
+  "libio",
  "libunwind",
  "runtime",
+  "satman"
 ]

 [profile.release]
--- a/src/Makefile
+++ b/src/Makefile
@ -1,16 +1,20 @@
 TARGET := zc706
 GWARGS := -V simple

-all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
+all: runtime
+
+runtime_target: ../build/runtime.bin
+
+satman_target: ../build/satman.bin

 .PHONY: all


-../build/pl.rs ../build/rustc-cfg: gateware/*
+../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/* 
 	mkdir -p ../build
-	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg $(GWARGS)
+	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)

-../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -print)
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
 	cd runtime && \
 	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
 	cargo xbuild --release \
@ -19,3 +23,13 @@ all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin

 ../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
 	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
+
+../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
+	cd satman && \
+	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
+	cargo xbuild --release \
+		--target-dir ../../build/firmware \
+		--no-default-features --features=target_$(TARGET)
+
+../build/satman.bin: ../build/firmware/armv7-none-eabihf/release/satman
+	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin
--- a/src/gateware/aux_controller.py
+++ b/src/gateware/aux_controller.py
@ -0,0 +1,85 @@
+"""Auxiliary controller, common to satellite and master"""
+
+from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
+from migen.fhdl.simplify import FullMemoryWE
+from misoc.interconnect.csr import *
+from migen_axi.interconnect.sram import SRAM
+from migen_axi.interconnect import axi
+
+max_packet = 1024
+
+class _DRTIOAuxControllerBase(Module):
+    def __init__(self, link_layer):
+        self.bus = axi.Interface()
+        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
+        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
+
+    def get_csrs(self):
+        return self.transmitter.get_csrs() + self.receiver.get_csrs()
+
+
+# TODO: FullMemoryWE should be applied by migen.build
+@FullMemoryWE()
+class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
+    def __init__(self, link_layer):
+        _DRTIOAuxControllerBase.__init__(self, link_layer)
+
+        tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
+        rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
+        aw_decoder = axi.AddressDecoder(self.bus.aw,
+            [(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.aw),
+             (lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.aw)],
+            register=True)
+        ar_decoder = axi.AddressDecoder(self.bus.ar,
+            [(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.ar),
+             (lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.ar)],
+            register=True)
+        # unlike wb, axi address decoder only connects ar/aw lanes,
+        # the rest must also be connected!
+        # not quite unlike an address decoder itself.
+
+        # connect bus.b with tx.b
+        self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
+                      self.bus.b.id.eq(tx_sdram_if.bus.b.id),
+                      self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
+                      self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
+        # connect bus.w with tx.w
+        # no worries about w.valid and slave sel here, only tx will be written to
+        self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
+                      tx_sdram_if.bus.w.data.eq(self.bus.w.data),
+                      tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
+                      tx_sdram_if.bus.w.last.eq(self.bus.w.last),
+                      tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
+                      self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
+        # connect bus.r with rx.r and tx.r w/o data
+        self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
+                #self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
+                self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
+                self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
+                self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
+                rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
+                tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
+        # connect read data after being masked
+        masked = [Replicate(rx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & rx_sdram_if.bus.r.data,
+                 Replicate(tx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & tx_sdram_if.bus.r.data]
+        self.comb += self.bus.r.data.eq(reduce(or_, masked))
+
+        self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
+
+
+@FullMemoryWE()
+class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
+    # Barebones version of the AuxController. No SRAM, no decoders.
+    # add memories manually from tx and rx in target code.
+    def get_tx_port(self):
+        return self.transmitter.mem.get_port(write_capable=True)
+
+    def get_rx_port(self):
+        return self.receiver.mem.get_port(write_capable=False)
+
+    def get_mem_size(self):
+        return max_packet
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -16,10 +16,15 @@ from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
 from artiq.gateware.rtio.phy import ttl_simple

+from artiq.gateware.drtio.transceiver import gtx_7series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+
 import dma
 import analyzer
 import acpki
-
+import aux_controller

 class RTIOCRG(Module, AutoCSR):
    def __init__(self, platform):
@ -71,6 +76,36 @@ class RTIOCRG(Module, AutoCSR):
        ]


+class _RTIOClockMultiplier(Module, AutoCSR):
+    def __init__(self, rtio_clk_freq):
+        self.pll_reset = CSRStorage(reset=1)
+        self.pll_locked = CSRStatus()
+        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
+
+        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
+        clkfbout = Signal()
+        clkfbin = Signal()
+        rtiox4_clk = Signal()
+        pll_locked = Signal()
+        self.specials += [
+            Instance("MMCME2_BASE",
+                p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
+                i_CLKIN1=ClockSignal("rtio"),
+                i_RST=self.pll_reset.storage,
+                o_LOCKED=pll_locked,
+
+                p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
+
+                o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
+
+                p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
+            ),
+            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
+            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
+
+            MultiReg(pll_locked, self.pll_locked.status)
+        ]
+        
 eem_iostandard_dict = {
     0: "LVDS_25",
     1: "LVDS_25",
@ -173,13 +208,295 @@ class GenericStandalone(SoCCore):


 class GenericMaster(SoCCore):
-    def __init__(self, description, **kwargs):
-        raise NotImplementedError
+    def __init__(self, description, acpki=False):
+        sys_clk_freq = 125e6
+
+        self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+
+        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+
+        # kasli_soc has no SATA, but it has 4x SFP
+        # not sure yet why sfp0 is omitted in MasterMode
+        data_pads = [platform.request("sfp", i) for i in range(4)]
+
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("clk125_gtp"),
+            pads=data_pads,
+            sys_clk_freq=sys_clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.submodules.rtio_crg = RTIOCRG(self.platform)
+        self.csr_devices.append("rtio_crg")
+        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
+        self.platform.add_false_path_constraints(
+            self.ps7.cd_sys.clk,
+            self.rtio_crg.cd_rtio.clk)
+
+        self.rtio_channels = []
+        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
+        if has_grabber:
+            self.grabber_csr_group = []
+        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
+
+        drtio_csr_group = []
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        self.drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtio_csr_group.append(core_name)
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
+            setattr(self.submodules, core_name, core)
+            self.drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            size = coreaux.get_mem_size()
+            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
+            self.axi2csr.register_port(coreaux.get_rx_port(), size)
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
+        self.rustc_cfg["has_drtio"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
+        self.add_csr_group("drtio", drtio_csr_group)
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.rustc_cfg["ki_impl"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.rustc_cfg["ki_impl"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri] + self.drtio_cri,
+            enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        if has_grabber:
+            self.rustc_cfg["has_grabber"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+            for grabber in self.grabber_csr_group:
+                self.platform.add_false_path_constraints(
+                    self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)


 class GenericSatellite(SoCCore):
-    def __init__(self, description, **kwargs):
-        raise NotImplementedError
+    def __init__(self, description, acpki=False):
+        sys_clk_freq = 125e6  
+        rtio_clk_freq = 125e6
+
+        self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+
+        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
+        self.csr_devices.append("rtio_crg")
+        
+        data_pads = [platform.request("sfp", i) for i in range(4)]
+        
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("clk125_gtp"),  
+            pads=data_pads,
+            sys_clk_freq=sys_clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        self.rtio_channels = []
+        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
+        if has_grabber:
+            self.grabber_csr_group = []
+        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
+
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtiorep_csr_group = []
+        self.drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            if i == 0:
+                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
+                core = cdr(DRTIOSatellite(
+                    self.rtio_tsc, self.drtio_transceiver.channels[i],
+                    self.rx_synchronizer))
+                self.submodules.drtiosat = core
+                self.csr_devices.append("drtiosat")
+            else:
+                corerep_name = "drtiorep" + str(i-1)
+                drtiorep_csr_group.append(corerep_name)
+
+                core = cdr(DRTIORepeater(
+                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
+                setattr(self.submodules, corerep_name, core)
+                self.drtio_cri.append(core.cri)
+                self.csr_devices.append(corerep_name)
+
+            coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            tx_port = coreaux.get_tx_port()
+            rx_port = coreaux.get_rx_port()
+            memory_address = self.axi2csr.register_port(tx_port, mem_size)
+            # rcv in upper half of the memory, thus added second
+            self.axi2csr.register_port(rx_port, mem_size)
+            # and registered in PS interface
+            # manually, because software refers to rx/tx by halves of entire memory block, not names
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.rustc_cfg["has_drtio"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+        self.add_csr_group("drtiorep", drtiorep_csr_group)
+
+        if self.acpki:
+            self.rustc_cfg["ki_impl"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.rustc_cfg["ki_impl"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
+        self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.drtiosat.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            mode="sync", enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")     
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        rtio_clk_period = 1e9/rtio_clk_freq
+        self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
+
+        self.submodules.siphaser = SiPhaser7Series(
+            si5324_clkin=platform.request("cdr_clk"),
+            rx_synchronizer=self.rx_synchronizer,
+            ultrascale=False,
+            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
+        self.csr_devices.append("siphaser")
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["has_siphaser"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
+
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            gtx0.txoutclk, gtx0.rxoutclk)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.crg.cd_sys.clk, gtx.rxoutclk)
+
+        if has_grabber:
+            self.rustc_cfg["has_grabber"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+            # no RTIO CRG here
+     
+
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))


 def write_csr_file(soc, filename):
@ -204,6 +521,8 @@ def main():
        help="build Rust interface into the specified file")
    parser.add_argument("-c", default=None,
        help="build Rust compiler configuration into the specified file")
+    parser.add_argument("-m", default=None,
+        help="build Rust memory interface into the specified file")
    parser.add_argument("-g", default=None,
        help="build gateware into the specified directory")
    parser.add_argument("--acpki", default=False, action="store_true",
@ -230,6 +549,8 @@ def main():

    if args.r is not None:
        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
    if args.c is not None:
        write_rustc_cfg_file(soc, args.c)
    if args.g is not None:
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@ -11,14 +11,20 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
+from misoc.cores import gpio

 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2

+from artiq.gateware.drtio.transceiver import gtx_7series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+
 import dma
 import analyzer
 import acpki
-
+import aux_controller

 class RTIOCRG(Module, AutoCSR):
    def __init__(self, platform, rtio_internal_clk):
@ -64,23 +70,88 @@ class RTIOCRG(Module, AutoCSR):
        ]


+class _RTIOClockMultiplier(Module, AutoCSR):
+    def __init__(self, rtio_clk_freq):
+        self.pll_reset = CSRStorage(reset=1)
+        self.pll_locked = CSRStatus()
+        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
+
+        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
+        clkfbout = Signal()
+        clkfbin = Signal()
+        rtiox4_clk = Signal()
+        pll_locked = Signal()
+        self.specials += [
+            Instance("MMCME2_BASE",
+                p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
+                i_CLKIN1=ClockSignal("rtio"),
+                i_RST=self.pll_reset.storage,
+                o_LOCKED=pll_locked,
+
+                p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
+
+                o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
+
+                p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
+            ),
+            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
+            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
+
+            MultiReg(pll_locked, self.pll_locked.status)
+        ]
+
+
+def fix_serdes_timing_path(platform):
+    # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
+    platform.add_platform_command(
+        "set_false_path -quiet "
+        "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
+            "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
+        "-to [get_pins -filter {{REF_PIN_NAME == D}} "
+            "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
+    )
+
+
+# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
+# This also changes the I/O standard for some on-board LEDs.
+leds_fmc33 = [
+    ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
+    ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
+]
+
+# same deal as with LEDs - changed I/O standard.
+si5324_fmc33 = [
+    ("si5324_33", 0,
+        Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")),
+        Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33"))
+    ),
+]
+
+
+def prepare_zc706_platform(platform):
+    platform.toolchain.bitstream_commands.extend([
+        "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+    ])
+    platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+    platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+    return platform
+
+
 class ZC706(SoCCore):
    def __init__(self, acpki=False):
        self.acpki = acpki
        self.rustc_cfg = dict()

        platform = zc706.Platform()
-        platform.toolchain.bitstream_commands.extend([
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
+        platform = prepare_zc706_platform(platform)
+
        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
        self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
        self.csr_devices.append("rtio_crg")
        self.rustc_cfg["has_rtio_crg_clock_sel"] = None
@ -122,10 +193,284 @@ class ZC706(SoCCore):
        self.csr_devices.append("rtio_analyzer")


-class Simple(ZC706):
-    def __init__(self, **kwargs):
-        ZC706.__init__(self, **kwargs)
+class _MasterBase(SoCCore):
+    def __init__(self, acpki=False, use_si5324_33=False):
+        self.acpki = acpki
+        self.rustc_cfg = dict()

+        platform = zc706.Platform()
+        platform = prepare_zc706_platform(platform)
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+
+        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+
+        if use_si5324_33:
+            platform.add_extension(si5324_fmc33)
+
+        self.sys_clk_freq = 125e6
+
+        platform = self.platform
+
+        self.comb += platform.request("sfp_tx_disable_n").eq(1)
+        data_pads = [
+            platform.request("sfp")
+        ]
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            pads=data_pads,
+            sys_clk_freq=self.sys_clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
+
+        drtio_csr_group = []
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        self.drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtio_csr_group.append(core_name)
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(
+                self.rtio_tsc, self.drtio_transceiver.channels[i]))
+            setattr(self.submodules, core_name, core)
+            self.drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
+            self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.rustc_cfg["has_drtio"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
+        self.add_csr_group("drtio", drtio_csr_group)
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+
+        if use_si5324_33:
+            self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
+        else:
+            self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["si5324_as_synthesizer"] = None
+
+        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.ps7.cd_sys.clk,
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
+
+        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
+        self.csr_devices.append("rtio_crg")
+        fix_serdes_timing_path(self.platform)
+
+    def add_rtio(self, rtio_channels):
+        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.rustc_cfg["ki_impl"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.rustc_cfg["ki_impl"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            mode="sync", enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+
+class _SatelliteBase(SoCCore):
+    def __init__(self, acpki=False, use_si5324_33=False):
+        self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        platform = zc706.Platform()
+        platform = prepare_zc706_platform(platform)
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+
+        if use_si5324_33:
+            platform.add_extension(si5324_fmc33)
+
+        self.sys_clk_freq = 125e6
+        platform = self.platform
+
+        # SFP
+        self.comb += platform.request("sfp_tx_disable_n").eq(0)
+        data_pads = [
+            platform.request("sfp")
+        ]
+
+        self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            pads=data_pads,
+            sys_clk_freq=self.sys_clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        self.drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            # Satellite
+            if i == 0:
+                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
+                core = cdr(DRTIOSatellite(
+                    self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
+                self.submodules.drtiosat = core
+                self.csr_devices.append("drtiosat")
+            # Repeaters - there would be for i != 0 - however zc706 only has one SFP
+            # and no other means to connect to 
+
+            coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            tx_port = coreaux.get_tx_port()
+            rx_port = coreaux.get_rx_port()
+            memory_address = self.axi2csr.register_port(tx_port, mem_size)
+            # rcv in upper half of the memory, thus added second
+            self.axi2csr.register_port(rx_port, mem_size)
+            # and registered in PS interface
+            # manually, because software refers to rx/tx by halves of entire memory block, not names
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.rustc_cfg["has_drtio"] = None
+        # no repeaters - it does not have drtio routing support
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+
+        # Si5324 Phaser
+        self.submodules.siphaser = SiPhaser7Series(
+            si5324_clkin=platform.request("si5324_clkin"),
+            rx_synchronizer=self.rx_synchronizer,
+            ultrascale=False,
+            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
+        platform.add_false_path_constraints(
+            self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
+        self.csr_devices.append("siphaser")
+        if use_si5324_33:
+            self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
+        else:
+            self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["has_siphaser"] = None
+
+        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.ps7.cd_sys.clk,
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.ps7.cd_sys.clk, gtx.rxoutclk)
+
+        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
+        self.csr_devices.append("rtio_crg")
+        fix_serdes_timing_path(self.platform)
+
+    def add_rtio(self, rtio_channels):
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        if self.acpki:
+            self.rustc_cfg["ki_impl"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.rustc_cfg["ki_impl"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.drtiosat.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            mode="sync", enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+
+class _Simple_RTIO:
+    def __init__(self):
        platform = self.platform

        rtio_channels = []
@ -140,23 +485,11 @@ class Simple(ZC706):
        self.add_rtio(rtio_channels)


-# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
-# This also changes the I/O standard for some on-board LEDs.
-leds_fmc33 = [
-    ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
-    ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
-    ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
-    ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
-]
-
-
-class NIST_CLOCK(ZC706):
+class _NIST_CLOCK_RTIO:
    """
    NIST clock hardware, with old backplane and 11 DDS channels
    """
-    def __init__(self, **kwargs):
-        ZC706.__init__(self, **kwargs)
-
+    def __init__(self):
        platform = self.platform
        platform.add_extension(nist_clock.fmc_adapter_io)
        platform.add_extension(leds_fmc33)
@ -203,14 +536,12 @@ class NIST_CLOCK(ZC706):
        self.add_rtio(rtio_channels)


-class NIST_QC2(ZC706):
+class _NIST_QC2_RTIO:
    """
    NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
    and 24 DDS channels.  Two backplanes are used.
    """
-    def __init__(self, **kwargs):
-        ZC706.__init__(self, **kwargs)
-
+    def __init__(self):
        platform = self.platform
        platform.add_extension(nist_qc2.fmc_adapter_io)
        platform.add_extension(leds_fmc33)
@ -253,7 +584,56 @@ class NIST_QC2(ZC706):
        self.add_rtio(rtio_channels)


-VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2]}
+class Simple(ZC706, _Simple_RTIO):
+    def __init__(self, acpki):
+        ZC706.__init__(self, acpki)
+        _Simple_RTIO.__init__(self)
+
+class Master(_MasterBase, _Simple_RTIO):
+    def __init__(self, acpki):
+        _MasterBase.__init__(self, acpki, use_si5324_33=False)
+        _Simple_RTIO.__init__(self)
+
+class Satellite(_SatelliteBase, _Simple_RTIO):
+    def __init__(self, acpki):
+        _SatelliteBase.__init__(self, acpki, use_si5324_33=False)
+        _Simple_RTIO.__init__(self)
+
+class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki):
+        ZC706.__init__(self, acpki)
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki):
+        _MasterBase.__init__(self, acpki, use_si5324_33=True)
+
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki):
+        _SatelliteBase.__init__(self, acpki, use_si5324_33=True)
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_QC2(ZC706, _NIST_QC2_RTIO):
+    def __init__(self, acpki):
+        ZC706.__init__(self, acpki)
+        _NIST_QC2_RTIO.__init__(self)
+
+class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
+    def __init__(self, acpki):
+        _MasterBase.__init__(self, acpki, use_si5324_33=True)
+        _NIST_QC2_RTIO.__init__(self)
+
+class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
+    def __init__(self, acpki):
+        _SatelliteBase.__init__(self, acpki, use_si5324_33=True)
+        _NIST_QC2_RTIO.__init__(self)
+
+
+VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite, 
+                                                  NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}


 def write_csr_file(soc, filename):
@ -261,6 +641,11 @@ def write_csr_file(soc, filename):
        f.write(cpu_interface.get_csr_rust(
            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))

+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+

 def write_rustc_cfg_file(soc, filename):
    with open(filename, "w") as f:
@ -276,6 +661,8 @@ def main():
        description="ARTIQ port to the ZC706 Zynq development kit")
    parser.add_argument("-r", default=None,
        help="build Rust interface into the specified file")
+    parser.add_argument("-m", default=None,
+        help="build Rust memory interface into the specified file")
    parser.add_argument("-c", default=None,
        help="build Rust compiler configuration into the specified file")
    parser.add_argument("-g", default=None,
@ -300,11 +687,12 @@ def main():

    if args.r is not None:
        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
    if args.c is not None:
        write_rustc_cfg_file(soc, args.c)
    if args.g is not None:
        soc.build(build_dir=args.g)

-
 if __name__ == "__main__":
    main()
--- a/src/libboard_artiq/Cargo.toml
+++ b/src/libboard_artiq/Cargo.toml
@ -0,0 +1,31 @@
+[package]
+name = "libboard_artiq"
+version = "0.0.0"
+authors = ["M-Labs"]
+edition = "2018"
+
+[lib]
+name = "libboard_artiq"
+
+[features]
+target_zc706 = []
+target_kasli_soc = []
+
+[build-dependencies]
+build_zynq = { path = "../libbuild_zynq" }
+
+[dependencies]
+log = "0.4"
+log_buffer = { version = "1.2" }
+crc = { version = "1.7", default-features = false }
+core_io = { version = "0.1", features = ["collections"] }
+embedded-hal = "0.2"
+nb = "1.0"
+void = { version = "1", default-features = false }
+
+io = { path = "../libio", features = ["byteorder"] }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
--- a/src/libboard_artiq/build.rs
+++ b/src/libboard_artiq/build.rs
@ -0,0 +1,5 @@
+extern crate build_zynq;
+
+fn main() {
+    build_zynq::cfg();
+}
--- a/src/libboard_artiq/src/drtio_routing.rs
+++ b/src/libboard_artiq/src/drtio_routing.rs
@ -0,0 +1,109 @@
+use libconfig::Config;
+#[cfg(has_drtio_routing)]
+use crate::pl::csr;
+use core::fmt;
+
+use log::{warn, info};
+
+#[cfg(has_drtio_routing)]
+pub const DEST_COUNT: usize = 256;
+#[cfg(not(has_drtio_routing))]
+pub const DEST_COUNT: usize = 0;
+pub const MAX_HOPS: usize = 32;
+pub const INVALID_HOP: u8 = 0xff;
+
+pub struct RoutingTable(pub [[u8; MAX_HOPS]; DEST_COUNT]);
+
+impl RoutingTable {
+    // default routing table is for star topology with no repeaters
+    pub fn default_master(default_n_links: usize) -> RoutingTable {
+        let mut ret = RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT]);
+        let n_entries = default_n_links + 1;  // include local RTIO
+        for i in 0..n_entries {
+            ret.0[i][0] = i as u8;
+        }
+        for i in 1..n_entries {
+            ret.0[i][1] = 0x00;
+        }
+        ret
+    }
+
+    // use this by default on satellite, as they receive
+    // the routing table from the master
+    pub fn default_empty() -> RoutingTable {
+        RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT])
+    }
+}
+
+impl fmt::Display for RoutingTable {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "RoutingTable {{")?;
+        for i in 0..DEST_COUNT {
+            if self.0[i][0] != INVALID_HOP {
+                write!(f, " {}:", i)?;
+                for j in 0..MAX_HOPS {
+                    if self.0[i][j] == INVALID_HOP {
+                        break;
+                    }
+                    write!(f, " {}", self.0[i][j])?;
+                }
+                write!(f, ";")?;
+            }
+        }
+        write!(f, " }}")?;
+        Ok(())
+    }
+}
+
+pub fn config_routing_table(default_n_links: usize, cfg: &Config) -> RoutingTable {
+    let mut ret = RoutingTable::default_master(default_n_links);
+    if let Ok(data) = cfg.read("routing_table") {
+        if data.len() == DEST_COUNT*MAX_HOPS
+        {
+            for i in 0..DEST_COUNT {
+                for j in 0..MAX_HOPS {
+                    ret.0[i][j] = data[i*MAX_HOPS+j];
+                }
+            }
+        }
+        else {
+            warn!("length of the routing table is incorrect, using default");
+        }
+    }
+    else {
+        warn!("could not read routing table from configuration, using default");
+    }
+    info!("routing table: {}", ret);
+    ret
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_enable(routing_table: &RoutingTable, rank: u8, destination: u8) {
+    let hop = routing_table.0[destination as usize][rank as usize];
+    unsafe {
+        csr::routing_table::destination_write(destination);
+        csr::routing_table::hop_write(hop);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_disable(destination: u8) {
+    unsafe {
+        csr::routing_table::destination_write(destination);
+        csr::routing_table::hop_write(INVALID_HOP);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_enable_all(routing_table: &RoutingTable, rank: u8) {
+    for i in 0..DEST_COUNT {
+        interconnect_enable(routing_table, rank, i as u8);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_disable_all() {
+    for i in 0..DEST_COUNT {
+        interconnect_disable(i as u8);
+    }
+}
--- a/src/libboard_artiq/src/drtioaux.rs
+++ b/src/libboard_artiq/src/drtioaux.rs
@ -0,0 +1,174 @@
+use crc;
+
+use core_io::{ErrorKind as IoErrorKind, Error as IoError};
+
+use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
+use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
+use crate::mem::mem::DRTIOAUX_MEM;
+use crate::pl::csr::DRTIOAUX;
+use crate::drtioaux_proto::Error as ProtocolError;
+
+pub use crate::drtioaux_proto::Packet;
+
+#[derive(Debug)]
+pub enum Error {
+    GatewareError,
+    CorruptedPacket,
+
+    LinkDown,
+    TimedOut,
+    UnexpectedReply,
+
+    RoutingError,
+
+    Protocol(ProtocolError)
+}
+
+impl From<ProtocolError> for Error {
+    fn from(value: ProtocolError) -> Error {
+        Error::Protocol(value)
+    }
+}
+
+impl From<IoError> for Error {
+    fn from(value: IoError) -> Error {
+        Error::Protocol(ProtocolError::Io(value))
+    }
+}
+
+pub fn reset(linkno: u8) {
+    let linkno = linkno as usize;
+    unsafe {
+        // clear buffer first to limit race window with buffer overflow
+        // error. We assume the CPU is fast enough so that no two packets
+        // will be received between the buffer and the error flag are cleared.
+        (DRTIOAUX[linkno].aux_rx_present_write)(1);
+        (DRTIOAUX[linkno].aux_rx_error_write)(1);
+    }
+}
+
+pub fn has_rx_error(linkno: u8) -> bool {
+    let linkno = linkno as usize;
+    unsafe {
+        let error = (DRTIOAUX[linkno].aux_rx_error_read)() != 0;
+        if error {
+            (DRTIOAUX[linkno].aux_rx_error_write)(1)
+        }
+        error
+    }
+}
+
+pub fn copy_with_swap(src: *mut u8, dst: *mut u8, len: isize) {
+    // for some reason, everything except checksum arrives
+    // with byte order swapped. and it must be sent as such too.
+    unsafe {
+        for i in (0..(len-4)).step_by(4) {
+            *dst.offset(i) = *src.offset(i+3);
+            *dst.offset(i+1) = *src.offset(i+2);
+            *dst.offset(i+2) = *src.offset(i+1);
+            *dst.offset(i+3) = *src.offset(i);
+        }
+        // checksum untouched
+        // unrolled for performance
+        *dst.offset(len-4) = *src.offset(len-4);
+        *dst.offset(len-3) = *src.offset(len-3);
+        *dst.offset(len-2) = *src.offset(len-2);
+        *dst.offset(len-1) = *src.offset(len-1);
+    }
+}
+
+fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
+    where F: FnOnce(&[u8]) -> Result<T, Error>
+{
+    let linkidx = linkno as usize;
+    unsafe {
+        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
+            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8;
+            let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
+            // work buffer, as byte order will need to be swapped, cannot be in place
+            let mut buf: [u8; 1024] = [0; 1024];
+            copy_with_swap(ptr, buf.as_mut_ptr(), len as isize);
+            let result = f(&buf[0..len]);
+            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
+            Ok(Some(result?))
+        } else {
+            Ok(None)
+        }
+    }
+}
+
+pub fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
+    if has_rx_error(linkno) {
+        return Err(Error::GatewareError)
+    }
+
+    receive(linkno, |buffer| {
+        if buffer.len() < 8 {
+            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into())
+        }
+
+        let mut reader = Cursor::new(buffer);
+
+        let checksum_at = buffer.len() - 4;
+        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
+        reader.set_position(checksum_at);
+        if reader.read_u32()? != checksum {
+            return Err(Error::CorruptedPacket)
+        }
+        reader.set_position(0);
+
+        Ok(Packet::read_from(&mut reader)?)
+    })
+}
+
+pub fn recv_timeout(linkno: u8, timeout_ms: Option<u64>,
+    timer: GlobalTimer) -> Result<Packet, Error> 
+{
+    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
+    let limit = timer.get_time() + timeout_ms;
+    while timer.get_time() < limit {
+        match recv(linkno)? {
+            None => (),
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
+    where F: FnOnce(&mut [u8]) -> Result<usize, Error>
+{
+    let linkno = linkno as usize;
+    unsafe {
+        while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
+        let ptr = DRTIOAUX_MEM[linkno].base as *mut u8;
+        let len = DRTIOAUX_MEM[linkno].size / 2;
+        // work buffer, works with unaligned mem access
+        let mut buf: [u8; 1024] = [0; 1024]; 
+        let len = f(&mut buf[0..len])?;
+        copy_with_swap(buf.as_mut_ptr(), ptr, len as isize);
+        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
+        (DRTIOAUX[linkno].aux_tx_write)(1);
+        Ok(())
+    }
+}
+
+pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
+    transmit(linkno, |buffer| {
+        let mut writer = Cursor::new(buffer);
+
+        packet.write_to(&mut writer)?;
+        
+        let padding = 4 - (writer.position() % 4);
+        if padding != 4 {
+            for _ in 0..padding {
+                writer.write_u8(0)?;
+            }
+        }
+
+        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
+        writer.write_u32(checksum)?;
+
+        Ok(writer.position())
+    })
+}
--- a/src/libboard_artiq/src/drtioaux_async.rs
+++ b/src/libboard_artiq/src/drtioaux_async.rs
@ -0,0 +1,139 @@
+use crc;
+
+use core_io::{ErrorKind as IoErrorKind, Error as IoError};
+use void::Void;
+use nb;
+
+use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
+use libasync::{task, block_async};
+
+use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
+use crate::mem::mem::DRTIOAUX_MEM;
+use crate::pl::csr::DRTIOAUX;
+use crate::drtioaux::{Error, has_rx_error, copy_with_swap};
+
+pub use crate::drtioaux_proto::Packet;
+
+pub async fn reset(linkno: u8) {
+    let linkno = linkno as usize;
+    unsafe {
+        // clear buffer first to limit race window with buffer overflow
+        // error. We assume the CPU is fast enough so that no two packets
+        // will be received between the buffer and the error flag are cleared.
+        (DRTIOAUX[linkno].aux_rx_present_write)(1);
+        (DRTIOAUX[linkno].aux_rx_error_write)(1);
+    }
+}
+
+fn tx_ready(linkno: usize) -> nb::Result<(), Void> {
+    unsafe {
+        if (DRTIOAUX[linkno].aux_tx_read)() != 0 {
+            Err(nb::Error::WouldBlock)
+        }
+        else {
+            Ok(())
+        }
+    }
+}
+
+async fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
+    where F: FnOnce(&[u8]) -> Result<T, Error>
+{
+    let linkidx = linkno as usize;
+    unsafe {
+        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
+            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8;
+            let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
+            // work buffer, as byte order will need to be swapped, cannot be in place
+            let mut buf: [u8; 1024] = [0; 1024];
+            copy_with_swap(ptr, buf.as_mut_ptr(), len as isize);
+            let result = f(&buf[0..len]);
+            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
+            Ok(Some(result?))
+        } else {
+            Ok(None)
+        }
+    }
+}
+
+pub async fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
+    if has_rx_error(linkno) {
+        return Err(Error::GatewareError)
+    }
+
+    receive(linkno, |buffer| {
+        if buffer.len() < 8 {
+            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into())
+        }
+
+        let mut reader = Cursor::new(buffer);
+
+        let checksum_at = buffer.len() - 4;
+        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
+        reader.set_position(checksum_at);
+        if reader.read_u32()? != checksum {
+            return Err(Error::CorruptedPacket)
+        }
+        reader.set_position(0);
+
+        Ok(Packet::read_from(&mut reader)?)
+    }).await
+}
+
+pub async fn recv_timeout(linkno: u8, timeout_ms: Option<u64>,
+    timer: GlobalTimer) -> Result<Packet, Error> 
+{
+    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
+    let limit = timer.get_time() + timeout_ms;
+    let mut would_block = false;
+    while timer.get_time() < limit {
+        // to ensure one last time recv would run one last time
+        // in case async would return after timeout
+        if would_block {
+            task::r#yield().await;
+        }
+        match recv(linkno).await? {
+            None => { would_block = true; },
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+async fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
+    where F: FnOnce(&mut [u8]) -> Result<usize, Error>
+{
+    let linkno = linkno as usize;
+    unsafe {
+        let _ = block_async!(tx_ready(linkno)).await;
+        let ptr = DRTIOAUX_MEM[linkno].base as *mut u8;
+        let len = DRTIOAUX_MEM[linkno].size / 2;
+        // work buffer, works with unaligned mem access
+        let mut buf: [u8; 1024] = [0; 1024]; 
+        let len = f(&mut buf[0..len])?;
+        copy_with_swap(buf.as_mut_ptr(), ptr, len as isize);
+        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
+        (DRTIOAUX[linkno].aux_tx_write)(1);
+        Ok(())
+    }
+}
+
+pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
+    transmit(linkno, |buffer| {
+        let mut writer = Cursor::new(buffer);
+
+        packet.write_to(&mut writer)?;
+        
+        let padding = 4 - (writer.position() % 4);
+        if padding != 4 {
+            for _ in 0..padding {
+                writer.write_u8(0)?;
+            }
+        }
+
+        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
+        writer.write_u32(checksum)?;
+
+        Ok(writer.position())
+    }).await
+}
--- a/src/libboard_artiq/src/drtioaux_proto.rs
+++ b/src/libboard_artiq/src/drtioaux_proto.rs
@ -0,0 +1,364 @@
+use core_io::{Write, Read, Error as IoError};
+
+use io::proto::{ProtoWrite, ProtoRead};
+
+#[derive(Debug)]
+pub enum Error {
+    UnknownPacket(u8),
+    Io(IoError)
+}
+
+impl From<IoError> for Error {
+    fn from(value: IoError) -> Error {
+        Error::Io(value)
+    }
+}
+
+#[derive(PartialEq, Debug)]
+pub enum Packet {
+    EchoRequest,
+    EchoReply,
+    ResetRequest,
+    ResetAck,
+    TSCAck,
+
+    DestinationStatusRequest { destination: u8 },
+    DestinationDownReply,
+    DestinationOkReply,
+    DestinationSequenceErrorReply { channel: u16 },
+    DestinationCollisionReply { channel: u16 },
+    DestinationBusyReply { channel: u16 },
+
+    RoutingSetPath { destination: u8, hops: [u8; 32] },
+    RoutingSetRank { rank: u8 },
+    RoutingAck,
+
+    MonitorRequest { destination: u8, channel: u16, probe: u8 },
+    MonitorReply { value: u32 },
+    InjectionRequest { destination: u8, channel: u16, overrd: u8, value: u8 },
+    InjectionStatusRequest { destination: u8, channel: u16, overrd: u8 },
+    InjectionStatusReply { value: u8 },
+
+    I2cStartRequest { destination: u8, busno: u8 },
+    I2cRestartRequest { destination: u8, busno: u8 },
+    I2cStopRequest { destination: u8, busno: u8 },
+    I2cWriteRequest { destination: u8, busno: u8, data: u8 },
+    I2cWriteReply { succeeded: bool, ack: bool },
+    I2cReadRequest { destination: u8, busno: u8, ack: bool },
+    I2cReadReply { succeeded: bool, data: u8 },
+    I2cBasicReply { succeeded: bool },
+
+    SpiSetConfigRequest { destination: u8, busno: u8, flags: u8, length: u8, div: u8, cs: u8 },
+    SpiWriteRequest { destination: u8, busno: u8, data: u32 },
+    SpiReadRequest { destination: u8, busno: u8 },
+    SpiReadReply { succeeded: bool, data: u32 },
+    SpiBasicReply { succeeded: bool },
+
+    JdacBasicRequest { destination: u8, dacno: u8, reqno: u8, param: u8 },
+    JdacBasicReply { succeeded: bool, retval: u8 },
+}
+
+impl Packet {
+    pub fn read_from<R>(reader: &mut R) -> Result<Self, Error>
+        where R: Read + ?Sized
+    {
+        Ok(match reader.read_u8()? {
+            0x00 => Packet::EchoRequest,
+            0x01 => Packet::EchoReply,
+            0x02 => Packet::ResetRequest,
+            0x03 => Packet::ResetAck,
+            0x04 => Packet::TSCAck,
+
+            0x20 => Packet::DestinationStatusRequest {
+                destination: reader.read_u8()?
+            },
+            0x21 => Packet::DestinationDownReply,
+            0x22 => Packet::DestinationOkReply,
+            0x23 => Packet::DestinationSequenceErrorReply {
+                channel: reader.read_u16()?
+            },
+            0x24 => Packet::DestinationCollisionReply {
+                channel: reader.read_u16()?
+            },
+            0x25 => Packet::DestinationBusyReply {
+                channel: reader.read_u16()?
+            },
+
+            0x30 => {
+                let destination = reader.read_u8()?;
+                let mut hops = [0; 32];
+                reader.read_exact(&mut hops)?;
+                Packet::RoutingSetPath {
+                    destination: destination,
+                    hops: hops
+                }
+            },
+            0x31 => Packet::RoutingSetRank {
+                rank: reader.read_u8()?
+            },
+            0x32 => Packet::RoutingAck,
+
+            0x40 => Packet::MonitorRequest {
+                destination: reader.read_u8()?,
+                channel: reader.read_u16()?,
+                probe: reader.read_u8()?
+            },
+            0x41 => Packet::MonitorReply {
+                value: reader.read_u32()?
+            },
+            0x50 => Packet::InjectionRequest {
+                destination: reader.read_u8()?,
+                channel: reader.read_u16()?,
+                overrd: reader.read_u8()?,
+                value: reader.read_u8()?
+            },
+            0x51 => Packet::InjectionStatusRequest {
+                destination: reader.read_u8()?,
+                channel: reader.read_u16()?,
+                overrd: reader.read_u8()?
+            },
+            0x52 => Packet::InjectionStatusReply {
+                value: reader.read_u8()?
+            },
+
+            0x80 => Packet::I2cStartRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?
+            },
+            0x81 => Packet::I2cRestartRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?
+            },
+            0x82 => Packet::I2cStopRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?
+            },
+            0x83 => Packet::I2cWriteRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?,
+                data: reader.read_u8()?
+            },
+            0x84 => Packet::I2cWriteReply {
+                succeeded: reader.read_bool()?,
+                ack: reader.read_bool()?
+            },
+            0x85 => Packet::I2cReadRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?,
+                ack: reader.read_bool()?
+            },
+            0x86 => Packet::I2cReadReply {
+                succeeded: reader.read_bool()?,
+                data: reader.read_u8()?
+            },
+            0x87 => Packet::I2cBasicReply {
+                succeeded: reader.read_bool()?
+            },
+
+            0x90 => Packet::SpiSetConfigRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?,
+                flags: reader.read_u8()?,
+                length: reader.read_u8()?,
+                div: reader.read_u8()?,
+                cs: reader.read_u8()?
+            },
+            /* 0x91: was Packet::SpiSetXferRequest */
+            0x92 => Packet::SpiWriteRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?,
+                data: reader.read_u32()?
+            },
+            0x93 => Packet::SpiReadRequest {
+                destination: reader.read_u8()?,
+                busno: reader.read_u8()?
+            },
+            0x94 => Packet::SpiReadReply {
+                succeeded: reader.read_bool()?,
+                data: reader.read_u32()?
+            },
+            0x95 => Packet::SpiBasicReply {
+                succeeded: reader.read_bool()?
+            },
+
+            0xa0 => Packet::JdacBasicRequest {
+                destination: reader.read_u8()?,
+                dacno: reader.read_u8()?,
+                reqno: reader.read_u8()?,
+                param: reader.read_u8()?,
+            },
+            0xa1 => Packet::JdacBasicReply {
+                succeeded: reader.read_bool()?,
+                retval: reader.read_u8()?
+            },
+
+            ty => return Err(Error::UnknownPacket(ty))
+        })
+    }
+
+    pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
+        where W: Write + ?Sized
+    {
+
+        match *self {
+            Packet::EchoRequest =>
+                writer.write_u8(0x00)?,
+            Packet::EchoReply =>
+                writer.write_u8(0x01)?,
+            Packet::ResetRequest =>
+                writer.write_u8(0x02)?,
+            Packet::ResetAck =>
+                writer.write_u8(0x03)?,
+            Packet::TSCAck =>
+                writer.write_u8(0x04)?,
+
+            Packet::DestinationStatusRequest { destination } => {
+                writer.write_u8(0x20)?;
+                writer.write_u8(destination)?;
+            },
+            Packet::DestinationDownReply =>
+                writer.write_u8(0x21)?,
+            Packet::DestinationOkReply =>
+                writer.write_u8(0x22)?,
+            Packet::DestinationSequenceErrorReply { channel } => {
+                writer.write_u8(0x23)?;
+                writer.write_u16(channel)?;
+            },
+            Packet::DestinationCollisionReply { channel } => {
+                writer.write_u8(0x24)?;
+                writer.write_u16(channel)?;
+            },
+            Packet::DestinationBusyReply { channel } => {
+                writer.write_u8(0x25)?;
+                writer.write_u16(channel)?;
+            },
+
+            Packet::RoutingSetPath { destination, hops } => {
+                writer.write_u8(0x30)?;
+                writer.write_u8(destination)?;
+                writer.write_all(&hops)?;
+            },
+            Packet::RoutingSetRank { rank } => {
+                writer.write_u8(0x31)?;
+                writer.write_u8(rank)?;
+            },
+            Packet::RoutingAck =>
+                writer.write_u8(0x32)?,
+
+            Packet::MonitorRequest { destination, channel, probe } => {
+                writer.write_u8(0x40)?;
+                writer.write_u8(destination)?;
+                writer.write_u16(channel)?;
+                writer.write_u8(probe)?;
+            },
+            Packet::MonitorReply { value } => {
+                writer.write_u8(0x41)?;
+                writer.write_u32(value)?;
+            },
+            Packet::InjectionRequest { destination, channel, overrd, value } => {
+                writer.write_u8(0x50)?;
+                writer.write_u8(destination)?;
+                writer.write_u16(channel)?;
+                writer.write_u8(overrd)?;
+                writer.write_u8(value)?;
+            },
+            Packet::InjectionStatusRequest { destination, channel, overrd } => {
+                writer.write_u8(0x51)?;
+                writer.write_u8(destination)?;
+                writer.write_u16(channel)?;
+                writer.write_u8(overrd)?;
+            },
+            Packet::InjectionStatusReply { value } => {
+                writer.write_u8(0x52)?;
+                writer.write_u8(value)?;
+            },
+
+            Packet::I2cStartRequest { destination, busno } => {
+                writer.write_u8(0x80)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+            },
+            Packet::I2cRestartRequest { destination, busno } => {
+                writer.write_u8(0x81)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+            },
+            Packet::I2cStopRequest { destination, busno } => {
+                writer.write_u8(0x82)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+            },
+            Packet::I2cWriteRequest { destination, busno, data } => {
+                writer.write_u8(0x83)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+                writer.write_u8(data)?;
+            },
+            Packet::I2cWriteReply { succeeded, ack } => {
+                writer.write_u8(0x84)?;
+                writer.write_bool(succeeded)?;
+                writer.write_bool(ack)?;
+            },
+            Packet::I2cReadRequest { destination, busno, ack } => {
+                writer.write_u8(0x85)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+                writer.write_bool(ack)?;
+            },
+            Packet::I2cReadReply { succeeded, data } => {
+                writer.write_u8(0x86)?;
+                writer.write_bool(succeeded)?;
+                writer.write_u8(data)?;
+            },
+            Packet::I2cBasicReply { succeeded } => {
+                writer.write_u8(0x87)?;
+                writer.write_bool(succeeded)?;
+            },
+
+            Packet::SpiSetConfigRequest { destination, busno, flags, length, div, cs } => {
+                writer.write_u8(0x90)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+                writer.write_u8(flags)?;
+                writer.write_u8(length)?;
+                writer.write_u8(div)?;
+                writer.write_u8(cs)?;
+            },
+            Packet::SpiWriteRequest { destination, busno, data } => {
+                writer.write_u8(0x92)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+                writer.write_u32(data)?;
+            },
+            Packet::SpiReadRequest { destination, busno } => {
+                writer.write_u8(0x93)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(busno)?;
+            },
+            Packet::SpiReadReply { succeeded, data } => {
+                writer.write_u8(0x94)?;
+                writer.write_bool(succeeded)?;
+                writer.write_u32(data)?;
+            },
+            Packet::SpiBasicReply { succeeded } => {
+                writer.write_u8(0x95)?;
+                writer.write_bool(succeeded)?;
+            },
+
+            Packet::JdacBasicRequest { destination, dacno, reqno, param } => {
+                writer.write_u8(0xa0)?;
+                writer.write_u8(destination)?;
+                writer.write_u8(dacno)?;
+                writer.write_u8(reqno)?;
+                writer.write_u8(param)?;
+            }
+            Packet::JdacBasicReply { succeeded, retval } => {
+                writer.write_u8(0xa1)?;
+                writer.write_bool(succeeded)?;
+                writer.write_u8(retval)?;
+            },
+        }
+        Ok(())
+    }
+    
+}
--- a/src/libboard_artiq/src/lib.rs
+++ b/src/libboard_artiq/src/lib.rs
@ -0,0 +1,68 @@
+#![no_std]
+#![feature(never_type)]
+
+extern crate log;
+extern crate crc;
+extern crate embedded_hal;
+extern crate core_io;
+extern crate io;
+extern crate libboard_zynq;
+extern crate libregister;
+extern crate libconfig;
+extern crate libcortex_a9;
+extern crate libasync;
+extern crate log_buffer;
+
+#[path = "../../../build/pl.rs"]
+pub mod pl;
+pub mod drtioaux_proto;
+pub mod drtio_routing;
+pub mod logger;
+#[cfg(has_si5324)]
+pub mod si5324;
+#[cfg(has_drtio)]
+pub mod drtioaux;
+#[cfg(has_drtio)]
+pub mod drtioaux_async;
+#[path = "../../../build/mem.rs"]
+pub mod mem;
+
+use core::{cmp, str};
+use libboard_zynq::slcr;
+use libregister::RegisterW;
+
+pub fn identifier_read(buf: &mut [u8]) -> &str {
+    unsafe {
+        pl::csr::identifier::address_write(0);
+        let len = pl::csr::identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            pl::csr::identifier::address_write(1 + i);
+            buf[i as usize] = pl::csr::identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}
+
+pub fn init_gateware() {
+    // Set up PS->PL clocks
+    slcr::RegisterBlock::unlocked(|slcr| {
+        // As we are touching the mux, the clock may glitch, so reset the PL.
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+                .fpga0_out_rst(true)
+                .fpga1_out_rst(true)
+                .fpga2_out_rst(true)
+                .fpga3_out_rst(true)
+        );
+        slcr.fpga0_clk_ctrl.write(
+            slcr::Fpga0ClkCtrl::zeroed()
+                .src_sel(slcr::PllSource::IoPll)
+                .divisor0(8)
+                .divisor1(1)
+        );
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+        );
+    });
+}
--- a/src/libboard_artiq/src/logger.rs
+++ b/src/libboard_artiq/src/logger.rs
--- a/src/libboard_artiq/src/si5324.rs
+++ b/src/libboard_artiq/src/si5324.rs
@ -3,14 +3,14 @@ use log::info;
 use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds};
 use embedded_hal::blocking::delay::DelayUs;
 #[cfg(not(si5324_soft_reset))]
-use pl::csr;
+use crate::pl::csr;

 type Result<T> = result::Result<T, &'static str>;

 const ADDRESS: u8 = 0x68;

 #[cfg(not(si5324_soft_reset))]
-fn hard_reset(timer: GlobalTimer) {
+fn hard_reset(timer: &mut GlobalTimer) {
    unsafe { csr::si5324_rst_n::out_write(0); }
    timer.delay_us(1_000);
    unsafe { csr::si5324_rst_n::out_write(1); }
@ -104,6 +104,7 @@ fn write(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
    Ok(())
 }

+#[allow(dead_code)]
 fn write_no_ack_value(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
    i2c.start().unwrap();
    if !i2c.write(ADDRESS << 1).unwrap() {
@ -146,8 +147,9 @@ fn ident(i2c: &mut I2c) -> Result<u16> {
 }

 #[cfg(si5324_soft_reset)]
-fn soft_reset(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
-    write_no_ack_value(i2c, 136, read(i2c, 136)? | 0x80)?;
+fn soft_reset(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
+    let val = read(i2c, 136)?;
+    write_no_ack_value(i2c, 136, val | 0x80)?;
    timer.delay_us(10_000);
    Ok(())
 }
@ -167,7 +169,7 @@ fn locked(i2c: &mut I2c) -> Result<bool> {
    Ok((read(i2c, 130)? & 0x01) == 0)  // LOL_INT=0
 }

-fn monitor_lock(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
+fn monitor_lock(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
    info!("waiting for Si5324 lock...");
    let timeout = timer.get_time() + Milliseconds(20_000);
    while !locked(i2c)? {
@ -180,7 +182,7 @@ fn monitor_lock(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
    Ok(())
 }

-fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
+fn init(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
    #[cfg(not(si5324_soft_reset))]
    hard_reset(timer);

@ -189,6 +191,10 @@ fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
        i2c.pca9548_select(0x70, 0)?;
        i2c.pca9548_select(0x71, 1 << 3)?;
    }
+    #[cfg(feature = "target_zc706")]
+    {
+        i2c.pca9548_select(0x74, 1 << 4)?;
+    }

    if ident(i2c)? != 0x0182 {
        return Err("Si5324 does not have expected product number");
@ -199,7 +205,7 @@ fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
    Ok(())
 }

-pub fn bypass(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
+pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
    let cksel_reg = match input {
        Input::Ckin1 => 0b00,
        Input::Ckin2 => 0b01,
@ -213,7 +219,7 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
    Ok(())
 }

-pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: GlobalTimer) -> Result<()> {
+pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
    let s = map_frequency_settings(settings)?;
    let cksel_reg = match input {
        Input::Ckin1 => 0b00,
@ -259,7 +265,7 @@ pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: G
    Ok(())
 }

-pub fn select_input(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
+pub fn select_input(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
    let cksel_reg = match input {
        Input::Ckin1 => 0b00,
        Input::Ckin2 => 0b01,
@ -270,4 +276,78 @@ pub fn select_input(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<(
    }
    monitor_lock(i2c, timer)?;
    Ok(())
+}
+
+#[cfg(has_siphaser)]
+pub mod siphaser {
+    use super::*;
+    use crate::pl::csr;
+
+    pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: &mut GlobalTimer) -> Result<()> {
+        let val = read(i2c, 3)?;
+        write(i2c, 3,   (val & 0xdf) | (1 << 5))?;  // DHOLD=1
+        unsafe {
+            csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
+        }
+        let val = read(i2c, 3)?;
+        write(i2c, 3,   (val & 0xdf) | (0 << 5))?;  // DHOLD=0
+        monitor_lock(i2c, timer)?;
+        Ok(())
+    }
+
+    fn phase_shift(direction: u8, timer: &mut GlobalTimer) {
+        unsafe {
+            csr::siphaser::phase_shift_write(direction);
+            while csr::siphaser::phase_shift_done_read() == 0 {}
+        }
+        // wait for the Si5324 loop to stabilize
+        timer.delay_us(500);
+    }
+
+    fn has_error(timer: &mut GlobalTimer) -> bool {
+        unsafe {
+            csr::siphaser::error_write(1);
+        }
+        timer.delay_us(5_000);
+        unsafe {
+            csr::siphaser::error_read() != 0
+        }
+    }
+
+    fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32> {
+        let mut nshifts = 0;
+
+        let mut previous = has_error(timer);
+        loop {
+            phase_shift(1, timer);
+            nshifts += 1;
+            let current = has_error(timer);
+            if previous != target && current == target {
+                return Ok(nshifts);
+            }
+            if nshifts > 5000 {
+                return Err("failed to find timing error edge");
+            }
+            previous = current;
+        }
+    }
+
+    pub fn calibrate_skew(timer: &mut GlobalTimer) -> Result<()> {
+        let jitter_margin = 32;
+        let lead = find_edge(false, timer)?;
+        for _ in 0..jitter_margin {
+            phase_shift(1, timer);
+        }
+        let width = find_edge(true, timer)? + jitter_margin;
+        // width is 360 degrees (one full rotation of the phase between s/h limits) minus jitter
+        info!("calibration successful, lead: {}, width: {} ({}deg)", lead, width, width*360/(56*8));
+
+        // Apply reverse phase shift for half the width to get into the
+        // middle of the working region.
+        for _ in 0..width/2 {
+            phase_shift(0, timer);
+        }
+
+        Ok(())
+    }
 }
--- a/src/libbuild_zynq/Cargo.toml
+++ b/src/libbuild_zynq/Cargo.toml
@ -0,0 +1,8 @@
+[package]
+authors = ["M-Labs"]
+name = "build_zynq"
+version = "0.0.0"
+
+[lib]
+name = "build_zynq"
+path = "lib.rs"
--- a/src/libbuild_zynq/lib.rs
+++ b/src/libbuild_zynq/lib.rs
@ -0,0 +1,13 @@
+use std::fs::File;
+use std::io::{BufRead, BufReader};
+
+pub fn cfg() {
+    // Handle rustc-cfg file
+    let cfg_path = "../../build/rustc-cfg";
+    println!("cargo:rerun-if-changed={}", cfg_path);
+
+    let f = BufReader::new(File::open(cfg_path).unwrap());
+    for line in f.lines() {
+        println!("cargo:rustc-cfg={}", line.unwrap());
+    }
+}
--- a/src/libio/Cargo.toml
+++ b/src/libio/Cargo.toml
@ -0,0 +1,17 @@
+[package]
+authors = ["M-Labs"]
+name = "io"
+version = "0.0.0"
+
+[lib]
+name = "io"
+path = "lib.rs"
+
+[dependencies]
+core_io = { version = "0.1", features = ["collections"] }
+byteorder = { version = "1.0", default-features = false, optional = true }
+
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+
+[features]
+alloc = []
--- a/src/libio/cursor.rs
+++ b/src/libio/cursor.rs
@ -0,0 +1,81 @@
+use core_io::{Read, Write, Error as IoError};
+
+#[derive(Debug, Clone)]
+pub struct Cursor<T> {
+    inner: T,
+    pos:   usize
+}
+
+impl<T> Cursor<T> {
+    #[inline]
+    pub fn new(inner: T) -> Cursor<T> {
+        Cursor { inner, pos: 0 }
+    }
+
+    #[inline]
+    pub fn into_inner(self) -> T {
+        self.inner
+    }
+
+    #[inline]
+    pub fn get_ref(&self) -> &T {
+        &self.inner
+    }
+
+    #[inline]
+    pub fn get_mut(&mut self) -> &mut T {
+        &mut self.inner
+    }
+
+    #[inline]
+    pub fn position(&self) -> usize {
+        self.pos
+    }
+
+    #[inline]
+    pub fn set_position(&mut self, pos: usize) {
+        self.pos = pos
+    }
+}
+
+impl<T: AsRef<[u8]>> Read for Cursor<T> {
+
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
+        let data = &self.inner.as_ref()[self.pos..];
+        let len = buf.len().min(data.len());
+        buf[..len].copy_from_slice(&data[..len]);
+        self.pos += len;
+        Ok(len)
+    }
+}
+
+impl Write for Cursor<&mut [u8]> {
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
+        let data = &mut self.inner[self.pos..];
+        let len  = buf.len().min(data.len());
+        data[..len].copy_from_slice(&buf[..len]);
+        self.pos += len;
+        Ok(len)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> Result<(), IoError> {
+        Ok(())
+    }
+}
+
+#[cfg(feature = "alloc")]
+impl Write for Cursor<::alloc::Vec<u8>> {
+
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
+        self.inner.extend_from_slice(buf);
+        Ok(buf.len())
+    }
+
+    #[inline]
+    fn flush(&mut self) -> Result<(), IoError> {
+        Ok(())
+    }
+}
--- a/src/libio/lib.rs
+++ b/src/libio/lib.rs
@ -0,0 +1,22 @@
+#![no_std]
+#![feature(never_type)]
+#![cfg_attr(feature = "alloc", feature(alloc))]
+
+extern crate alloc;
+extern crate core_io;
+
+#[cfg(feature = "alloc")]
+#[macro_use]
+use alloc;
+#[cfg(feature = "byteorder")]
+extern crate byteorder;
+
+pub mod cursor;
+#[cfg(feature = "byteorder")]
+pub mod proto;
+
+pub use cursor::Cursor;
+#[cfg(feature = "byteorder")]
+pub use proto::{ProtoRead, ProtoWrite};
+#[cfg(all(feature = "byteorder", feature = "alloc"))]
+pub use proto::ReadStringError;
--- a/src/runtime/src/proto_core_io.rs
+++ b/src/runtime/src/proto_core_io.rs
--- a/src/runtime/Cargo.toml
+++ b/src/runtime/Cargo.toml
@ -6,10 +6,13 @@ authors = ["M-Labs"]
 edition = "2018"

 [features]
-target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
-target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
+target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
+target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
 default = ["target_zc706"]

+[build-dependencies]
+build_zynq = { path = "../libbuild_zynq" }
+
 [dependencies]
 num-traits = { version = "0.2", default-features = false }
 num-derive = "0.3"
@ -37,3 +40,5 @@ dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
 unwind = { path = "../libunwind" }
 libc = { path = "../libc" }
+io = { path = "../libio" }
+libboard_artiq = { path = "../libboard_artiq" }
--- a/src/runtime/build.rs
+++ b/src/runtime/build.rs
@ -1,9 +1,10 @@
 use std::env;
 use std::fs::File;
 use std::io::Write;
-use std::io::{BufRead, BufReader};
 use std::path::PathBuf;

+extern crate build_zynq;
+
 fn main() {
    // Put the linker script somewhere the linker can find it
    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -16,13 +17,5 @@ fn main() {
    // Only re-run the build script when link.x is changed,
    // instead of when any part of the source code changes.
    println!("cargo:rerun-if-changed=link.x");
-
-    // Handle rustc-cfg file
-    let cfg_path = "../../build/rustc-cfg";
-    println!("cargo:rerun-if-changed={}", cfg_path);
-
-    let f = BufReader::new(File::open(cfg_path).unwrap());
-    for line in f.lines() {
-        println!("cargo:rustc-cfg={}", line.unwrap());
-    }
+    build_zynq::cfg();
 }
--- a/src/runtime/src/comms.rs
+++ b/src/runtime/src/comms.rs
@ -21,6 +21,7 @@ use libcortex_a9::{semaphore::Semaphore, mutex::Mutex, sync_channel::{Sender, Re
 use futures::{select_biased, future::FutureExt};
 use libasync::{smoltcp::{Sockets, TcpStream}, task};
 use libconfig::{Config, net_settings};
+use libboard_artiq::drtio_routing;

 use crate::proto_async::*;
 use crate::kernel;
@ -28,7 +29,8 @@ use crate::rpc;
 use crate::moninj;
 use crate::mgmt;
 use crate::analyzer;
-
+use crate::rtio_mgt;
+use crate::pl;

 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum Error {
@ -387,8 +389,21 @@ pub fn main(timer: GlobalTimer, cfg: Config) {

    Sockets::init(32);

+    // before, mutex was on io, but now that io isn't used...?
+    let aux_mutex: Rc<Mutex<bool>> = Rc::new(Mutex::new(false));
+    #[cfg(has_drtio)]
+    let drtio_routing_table = Rc::new(RefCell::new(
+        drtio_routing::config_routing_table(pl::csr::DRTIO.len(), &cfg)));
+    #[cfg(not(has_drtio))]
+    let drtio_routing_table = Rc::new(RefCell::new(drtio_routing::RoutingTable::default_empty()));
+    let up_destinations = Rc::new(RefCell::new([false; drtio_routing::DEST_COUNT]));
+    #[cfg(has_drtio_routing)]
+    drtio_routing::interconnect_disable_all();
+
+    rtio_mgt::startup(&aux_mutex, &drtio_routing_table, &up_destinations, timer);
+
    analyzer::start();
-    moninj::start(timer);
+    moninj::start(timer, aux_mutex, drtio_routing_table);

    let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
    let idle_kernel = Rc::new(cfg.read("idle").ok());
--- a/src/runtime/src/main.rs
+++ b/src/runtime/src/main.rs
@ -11,82 +11,43 @@

 extern crate alloc;

-use core::{cmp, str};
 use log::{info, warn, error};

-use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr};
+use libboard_zynq::{timer::GlobalTimer, mpcore, gic};
 use libasync::{task, block_async};
 use libsupport_zynq::ram;
 use nb;
 use void::Void;
 use embedded_hal::blocking::delay::DelayMs;
 use libconfig::Config;
-use libregister::RegisterW;
 use libcortex_a9::l2c::enable_l2_cache;
+use libboard_artiq::{logger, identifier_read, init_gateware, pl};
+#[cfg(has_si5324)]
+use libboard_artiq::si5324;

-mod proto_core_io;
 mod proto_async;
 mod comms;
 mod rpc;
-#[path = "../../../build/pl.rs"]
-mod pl;
 #[cfg(ki_impl = "csr")]
 #[path = "rtio_csr.rs"]
 mod rtio;
 #[cfg(ki_impl = "acp")]
 #[path = "rtio_acp.rs"]
 mod rtio;
+mod rtio_mgt;
 mod kernel;
 mod moninj;
 mod eh_artiq;
 mod panic;
-mod logger;
 mod mgmt;
 mod analyzer;
 mod irq;
 mod i2c;
-#[cfg(has_si5324)]
-mod si5324;

-fn init_gateware() {
-    // Set up PS->PL clocks
-    slcr::RegisterBlock::unlocked(|slcr| {
-        // As we are touching the mux, the clock may glitch, so reset the PL.
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-                .fpga0_out_rst(true)
-                .fpga1_out_rst(true)
-                .fpga2_out_rst(true)
-                .fpga3_out_rst(true)
-        );
-        slcr.fpga0_clk_ctrl.write(
-            slcr::Fpga0ClkCtrl::zeroed()
-                .src_sel(slcr::PllSource::IoPll)
-                .divisor0(8)
-                .divisor1(1)
-        );
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-        );
-    });
-}
-
-fn identifier_read(buf: &mut [u8]) -> &str {
-    unsafe {
-        pl::csr::identifier::address_write(0);
-        let len = pl::csr::identifier::data_read();
-        let len = cmp::min(len, buf.len() as u8);
-        for i in 0..len {
-            pl::csr::identifier::address_write(1 + i);
-            buf[i as usize] = pl::csr::identifier::data_read();
-        }
-        str::from_utf8_unchecked(&buf[..len as usize])
-    }
-}
-
-fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
+fn init_rtio(timer: &mut GlobalTimer, _cfg: &Config) {
+    #[cfg(has_rtio_crg_clock_sel)]
    let clock_sel =
-        if let Ok(rtioclk) = cfg.read_str("rtioclk") {
+        if let Ok(rtioclk) = _cfg.read_str("rtioclk") {
            match rtioclk.as_ref() {
                "internal" => {
                    info!("using internal RTIO clock");
@ -130,6 +91,19 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
    }
 }

+#[cfg(has_drtio)]
+fn init_drtio(timer: &mut GlobalTimer)
+{
+    unsafe {
+        pl::csr::drtio_transceiver::stable_clkin_write(1);
+    }
+    timer.delay_ms(2); // wait for CPLL/QPLL lock
+    unsafe {
+        pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
+    }
+}
+
+
 fn wait_for_async_rtio_error() -> nb::Result<(), Void> {
    unsafe {
        if pl::csr::rtio_core::async_error_read() != 0 {
@ -201,7 +175,7 @@ pub fn main_core0() {
    i2c::init();
    #[cfg(has_si5324)]
    si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
-        &SI5324_SETTINGS, si5324::Input::Ckin2, timer).expect("cannot initialize Si5324");
+        &SI5324_SETTINGS, si5324::Input::Ckin2, &mut timer).expect("cannot initialize Si5324");

    let cfg = match Config::new() {
        Ok(cfg) => cfg,
@ -211,6 +185,9 @@ pub fn main_core0() {
        }
    };

+    #[cfg(has_drtio)]
+    init_drtio(&mut timer);
+
    init_rtio(&mut timer, &cfg);
    task::spawn(report_async_rtio_errors());

--- a/src/runtime/src/mgmt.rs
+++ b/src/runtime/src/mgmt.rs
@ -6,7 +6,7 @@ use core::cell::RefCell;
 use alloc::{rc::Rc, vec::Vec, string::String};
 use log::{self, info, debug, warn, error, LevelFilter};

-use crate::logger::{BufferLogger, LogBufferRef};
+use libboard_artiq::logger::{BufferLogger, LogBufferRef};
 use crate::proto_async::*;
 use num_derive::FromPrimitive;
 use num_traits::FromPrimitive;
--- a/src/runtime/src/moninj.rs
+++ b/src/runtime/src/moninj.rs
@ -1,17 +1,19 @@
-use core::fmt;
-use alloc::collections::BTreeMap;
-use log::{debug, info, warn};
+use core::{fmt, cell::RefCell};
+use alloc::{collections::BTreeMap, rc::Rc};
+use log::{debug, info, warn, error};
 use void::Void;

+use libboard_artiq::drtio_routing;
+
 use libboard_zynq::{smoltcp, timer::GlobalTimer, time::Milliseconds};
 use libasync::{task, smoltcp::TcpStream, block_async, nb};
+use libcortex_a9::mutex::Mutex;

 use num_derive::{FromPrimitive, ToPrimitive};
 use num_traits::{FromPrimitive, ToPrimitive};
 use futures::{pin_mut, select_biased, FutureExt};

 use crate::proto_async::*;
-use crate::pl::csr;


 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -19,7 +21,6 @@ pub enum Error {
    NetworkError(smoltcp::Error),
    UnexpectedPattern,
    UnrecognizedPacket,
-
 }

 pub type Result<T> = core::result::Result<T, Error>;
@ -54,32 +55,108 @@ enum DeviceMessage {
    InjectionStatus = 1
 }

-fn read_probe(channel: i32, probe: i8) -> i32 {
-    unsafe {
-        csr::rtio_moninj::mon_chan_sel_write(channel as _);
-        csr::rtio_moninj::mon_probe_sel_write(probe as _);
-        csr::rtio_moninj::mon_value_update_write(1);
-        csr::rtio_moninj::mon_value_read() as i32
+#[cfg(has_drtio)]
+mod remote_moninj {
+    use super::*;
+    use libboard_artiq::drtioaux;
+    use crate::rtio_mgt::drtio;
+
+    pub fn read_probe(aux_mutex: &Rc<Mutex<bool>>, timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, probe: i8) -> i32 {
+        let reply = task::block_on(drtio::aux_transact(aux_mutex, linkno, &drtioaux::Packet::MonitorRequest { 
+            destination: destination,
+            channel: channel as _,
+            probe: probe as _},
+            timer));
+        match reply {
+            Ok(drtioaux::Packet::MonitorReply { value }) => return value as i32,
+            Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
+            Err(e) => error!("aux packet error ({})", e)
+        }
+        0
+    }
+
+    pub fn inject(aux_mutex: &Rc<Mutex<bool>>, _timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, overrd: i8, value: i8) {
+        let _lock = aux_mutex.lock();
+        drtioaux::send(linkno, &drtioaux::Packet::InjectionRequest {
+            destination: destination,
+            channel: channel as _,
+            overrd: overrd as _,
+            value: value as _
+        }).unwrap();
+    }
+
+    pub fn read_injection_status(aux_mutex: &Rc<Mutex<bool>>, timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, overrd: i8) -> i8 {
+        let reply = task::block_on(drtio::aux_transact(aux_mutex, 
+            linkno, 
+            &drtioaux::Packet::InjectionStatusRequest {
+                destination: destination,
+                channel: channel as _,
+                overrd: overrd as _},
+            timer));
+        match reply {
+            Ok(drtioaux::Packet::InjectionStatusReply { value }) => return value as i8,
+            Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
+            Err(e) => error!("aux packet error ({})", e)
+        }
+        0
    }
 }

-fn inject(channel: i32, overrd: i8, value: i8) {
-    unsafe {
-        csr::rtio_moninj::inj_chan_sel_write(channel as _);
-        csr::rtio_moninj::inj_override_sel_write(overrd as _);
-        csr::rtio_moninj::inj_value_write(value as _);
+mod local_moninj {
+    use libboard_artiq::pl::csr;
+
+    pub fn read_probe(channel: i32, probe: i8) -> i32 {
+        unsafe {
+            csr::rtio_moninj::mon_chan_sel_write(channel as _);
+            csr::rtio_moninj::mon_probe_sel_write(probe as _);
+            csr::rtio_moninj::mon_value_update_write(1);
+            csr::rtio_moninj::mon_value_read() as i32
+        }
+    }
+
+    pub fn inject(channel: i32, overrd: i8, value: i8) {
+        unsafe {
+            csr::rtio_moninj::inj_chan_sel_write(channel as _);
+            csr::rtio_moninj::inj_override_sel_write(overrd as _);
+            csr::rtio_moninj::inj_value_write(value as _);
+        }
+    }
+
+    pub fn read_injection_status(channel: i32, overrd: i8) -> i8 {
+        unsafe {
+            csr::rtio_moninj::inj_chan_sel_write(channel as _);
+            csr::rtio_moninj::inj_override_sel_write(overrd as _);
+            csr::rtio_moninj::inj_value_read() as i8
+        }
    }
 }

-fn read_injection_status(channel: i32, overrd: i8) -> i8 {
-    unsafe {
-        csr::rtio_moninj::inj_chan_sel_write(channel as _);
-        csr::rtio_moninj::inj_override_sel_write(overrd as _);
-        csr::rtio_moninj::inj_value_read() as i8
-    }
+#[cfg(has_drtio)]
+macro_rules! dispatch {
+    ($timer:ident, $aux_mutex:ident, $routing_table:ident, $channel:expr, $func:ident $(, $param:expr)*) => {{
+        let destination = ($channel >> 16) as u8;
+        let channel = $channel;
+        let routing_table = $routing_table.borrow_mut();
+        let hop = routing_table.0[destination as usize][0];
+        if hop == 0 {
+            local_moninj::$func(channel.into(), $($param, )*)
+        } else {
+            let linkno = hop - 1 as u8;
+            remote_moninj::$func($aux_mutex, $timer, linkno, destination, channel, $($param, )*)
+        }
+    }}
 }

-async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()> {
+#[cfg(not(has_drtio))]
+macro_rules! dispatch {
+    ($timer:ident, $aux_mutex:ident, $routing_table:ident, $channel:expr, $func:ident $(, $param:expr)*) => {{
+        let channel = $channel as u16;
+        local_moninj::$func(channel, $($param, )*)
+    }}
+}
+
+async fn handle_connection(stream: &TcpStream, timer: GlobalTimer, 
+        _aux_mutex: &Rc<Mutex<bool>>, _routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>) -> Result<()> {
    if !expect(&stream, b"ARTIQ moninj\n").await? {
        return Err(Error::UnexpectedPattern);
    }
@ -135,13 +212,13 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()>
                        let channel = read_i32(&stream).await?;
                        let overrd = read_i8(&stream).await?;
                        let value = read_i8(&stream).await?;
-                        inject(channel, overrd, value);
+                        dispatch!(timer, _aux_mutex, _routing_table, channel, inject, overrd, value);
                        debug!("INJECT channel {}, overrd {}, value {}", channel, overrd, value);
                    },
                    HostMessage::GetInjectionStatus => {
                        let channel = read_i32(&stream).await?;
                        let overrd = read_i8(&stream).await?;
-                        let value = read_injection_status(channel, overrd);
+                        let value = dispatch!(timer, _aux_mutex, _routing_table, channel, read_injection_status, overrd);
                        write_i8(&stream, DeviceMessage::InjectionStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
                        write_i8(&stream, overrd).await?;
@ -151,7 +228,7 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()>
            },
            _ = timeout_f => {
                for (&(channel, probe), previous) in probe_watch_list.iter_mut() {
-                    let current = read_probe(channel, probe);
+                    let current = dispatch!(timer, _aux_mutex, _routing_table, channel, read_probe, probe);
                    if previous.is_none() || previous.unwrap() != current {
                        write_i8(&stream, DeviceMessage::MonitorStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
@ -161,7 +238,7 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()>
                    }
                }
                for (&(channel, overrd), previous) in inject_watch_list.iter_mut() {
-                    let current = read_injection_status(channel, overrd);
+                    let current = dispatch!(timer, _aux_mutex, _routing_table, channel, read_injection_status, overrd);
                    if previous.is_none() || previous.unwrap() != current {
                        write_i8(&stream, DeviceMessage::InjectionStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
@ -176,13 +253,15 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()>
    }
 }

-pub fn start(timer: GlobalTimer) {
+pub fn start(timer: GlobalTimer, aux_mutex: Rc<Mutex<bool>>, routing_table: Rc<RefCell<drtio_routing::RoutingTable>>) {
    task::spawn(async move {
        loop {
+            let aux_mutex = aux_mutex.clone();
+            let routing_table = routing_table.clone();
            let stream = TcpStream::accept(1383, 2048, 2048).await.unwrap();
            task::spawn(async move {
                info!("received connection");
-                let result = handle_connection(&stream, timer).await;
+                let result = handle_connection(&stream, timer, &aux_mutex, &routing_table).await;
                match result {
                    Err(Error::NetworkError(smoltcp::Error::Finished)) => info!("peer closed connection"),
                    Err(error) => warn!("connection terminated: {}", error),
--- a/src/runtime/src/rpc.rs
+++ b/src/runtime/src/rpc.rs
@ -10,7 +10,7 @@ use libasync::smoltcp::TcpStream;
 use alloc::boxed::Box;
 use async_recursion::async_recursion;

-use crate::proto_core_io::ProtoWrite;
+use io::proto::ProtoWrite;
 use crate::proto_async;
 use self::tag::{Tag, TagIterator, split_tag};

--- a/src/runtime/src/rtio_mgt.rs
+++ b/src/runtime/src/rtio_mgt.rs
@ -0,0 +1,351 @@
+use core::cell::RefCell;
+use alloc::rc::Rc;
+use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
+use libboard_artiq::{pl::csr, drtio_routing};
+use libcortex_a9::mutex::Mutex;
+
+
+#[cfg(has_drtio)]
+pub mod drtio {
+    use super::*;
+    use libboard_artiq::drtioaux_async;
+    use libboard_artiq::drtioaux_async::Packet;
+    use libboard_artiq::drtioaux::Error;
+    use log::{warn, error, info};
+    use embedded_hal::blocking::delay::DelayMs;
+    use libasync::{task, delay};
+
+    pub fn startup(aux_mutex: &Rc<Mutex<bool>>,
+            routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
+            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+            timer: GlobalTimer) {
+        let aux_mutex = aux_mutex.clone();
+        let routing_table = routing_table.clone();
+        let up_destinations = up_destinations.clone();
+        task::spawn(async move {
+            let routing_table = routing_table.borrow();
+            link_thread(&aux_mutex, &routing_table, &up_destinations, timer).await;
+        });
+    }
+
+    async fn link_rx_up(linkno: u8) -> bool {
+        let linkno = linkno as usize;
+        unsafe {
+            (csr::DRTIO[linkno].rx_up_read)() == 1
+        }
+    }
+
+    async fn recv_aux_timeout(linkno: u8, timeout: u64, timer: GlobalTimer) -> Result<Packet, &'static str> {
+        if !link_rx_up(linkno).await {
+            return Err("link went down");
+        }
+        match drtioaux_async::recv_timeout(linkno, Some(timeout), timer).await {
+            Ok(packet) => return Ok(packet),
+            Err(Error::TimedOut) => return Err("timed out"),
+            Err(_) => return Err("aux packet error"),
+        }
+    }
+
+    pub async fn aux_transact(aux_mutex: &Mutex<bool>, linkno: u8, request: &Packet,
+            timer: GlobalTimer) -> Result<Packet, &'static str> {
+        let _lock = aux_mutex.lock();
+        drtioaux_async::send(linkno, request).await.unwrap();
+        recv_aux_timeout(linkno, 200, timer).await
+    }
+
+    async fn drain_buffer(linkno: u8, draining_time: Milliseconds, timer: GlobalTimer) {
+        let max_time = timer.get_time() + draining_time;
+        loop {
+            if timer.get_time() > max_time {
+                return;
+            } //could this be cut short?
+            let _ = drtioaux_async::recv(linkno).await;
+        }
+    }
+
+    async fn ping_remote(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, timer: GlobalTimer) -> u32 {
+        let mut count = 0;
+        loop {
+            if !link_rx_up(linkno).await {
+                return 0
+            }
+            count += 1;
+            if count > 100 {
+                return 0;
+            }
+            let reply = aux_transact(aux_mutex, linkno, &Packet::EchoRequest, timer).await;
+            match reply {
+                Ok(Packet::EchoReply) => {
+                    // make sure receive buffer is drained
+                    let draining_time = Milliseconds(200);
+                    drain_buffer(linkno, draining_time, timer).await;
+                    return count;
+                }
+                _ => {}
+            }
+        }
+    }
+
+    async fn sync_tsc(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, timer: GlobalTimer) -> Result<(), &'static str> {
+        let _lock = aux_mutex.lock();
+
+        unsafe {
+            (csr::DRTIO[linkno as usize].set_time_write)(1);
+            while (csr::DRTIO[linkno as usize].set_time_read)() == 1 {}
+        }
+        // TSCAck is the only aux packet that is sent spontaneously
+        // by the satellite, in response to a TSC set on the RT link.
+        let reply = recv_aux_timeout(linkno, 10000, timer).await?;
+        if reply == Packet::TSCAck {
+            return Ok(());
+        } else {
+            return Err("unexpected reply");
+        }
+    }
+
+    async fn load_routing_table(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, routing_table: &drtio_routing::RoutingTable,
+        timer: GlobalTimer) -> Result<(), &'static str> {
+        for i in 0..drtio_routing::DEST_COUNT {
+            let reply = aux_transact(aux_mutex, linkno, &Packet::RoutingSetPath {
+                destination: i as u8,
+                hops: routing_table.0[i]
+            }, timer).await?;
+            if reply != Packet::RoutingAck {
+                return Err("unexpected reply");
+            }
+        }
+        Ok(())
+    }
+
+    async fn set_rank(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, rank: u8, timer: GlobalTimer) -> Result<(), &'static str> {
+        let reply = aux_transact(aux_mutex, linkno, &Packet::RoutingSetRank {
+            rank: rank
+        }, timer).await?;
+        if reply != Packet::RoutingAck {
+            return Err("unexpected reply");
+        }
+        Ok(())
+    }
+
+    async fn init_buffer_space(destination: u8, linkno: u8) {
+        let linkno = linkno as usize;
+        unsafe {
+            (csr::DRTIO[linkno].destination_write)(destination);
+            (csr::DRTIO[linkno].force_destination_write)(1);
+            (csr::DRTIO[linkno].o_get_buffer_space_write)(1);
+            while (csr::DRTIO[linkno].o_wait_read)() == 1 {}
+            info!("[DEST#{}] buffer space is {}",
+                destination, (csr::DRTIO[linkno].o_dbg_buffer_space_read)());
+            (csr::DRTIO[linkno].force_destination_write)(0);
+        }
+    }
+
+    async fn process_unsolicited_aux(aux_mutex: &Rc<Mutex<bool>>, linkno: u8) {
+        let _lock = aux_mutex.lock();
+        match drtioaux_async::recv(linkno).await {
+            Ok(Some(packet)) => warn!("[LINK#{}] unsolicited aux packet: {:?}", linkno, packet),
+            Ok(None) => (),
+            Err(_) => warn!("[LINK#{}] aux packet error", linkno)
+        }
+    }
+
+    async fn process_local_errors(linkno: u8) {
+        let errors;
+        let linkidx = linkno as usize;
+        unsafe {
+            errors = (csr::DRTIO[linkidx].protocol_error_read)();
+            (csr::DRTIO[linkidx].protocol_error_write)(errors);
+        }
+        if errors != 0 {
+            error!("[LINK#{}] error(s) found (0x{:02x}):", linkno, errors);
+            if errors & 1 != 0 {
+                error!("[LINK#{}] received packet of an unknown type", linkno);
+            }
+            if errors & 2 != 0 {
+                error!("[LINK#{}] received truncated packet", linkno);
+            }
+            if errors & 4 != 0 {
+                error!("[LINK#{}] timeout attempting to get remote buffer space", linkno);
+            }
+        }
+    }
+
+    async fn destination_set_up(routing_table: &drtio_routing::RoutingTable,
+            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+            destination: u8, up: bool) {
+        let mut up_destinations = up_destinations.borrow_mut();
+        up_destinations[destination as usize] = up;
+        if up {
+            drtio_routing::interconnect_enable(routing_table, 0, destination);
+            info!("[DEST#{}] destination is up", destination);
+        } else {
+            drtio_routing::interconnect_disable(destination);
+            info!("[DEST#{}] destination is down", destination);
+        }
+    }
+
+    async fn destination_up(up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, destination: u8) -> bool {
+        let up_destinations = up_destinations.borrow();
+        up_destinations[destination as usize]
+    }
+
+    async fn destination_survey(aux_mutex: &Rc<Mutex<bool>>, routing_table: &drtio_routing::RoutingTable,
+            up_links: &[bool],
+            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+            timer: GlobalTimer) {
+        for destination in 0..drtio_routing::DEST_COUNT {
+            let hop = routing_table.0[destination][0];
+            let destination = destination as u8;
+
+            if hop == 0 {
+                /* local RTIO */
+                if !destination_up(up_destinations, destination).await {
+                    destination_set_up(routing_table, up_destinations, destination, true).await;
+                }
+            } else if hop as usize <= csr::DRTIO.len() {
+                let linkno = hop - 1;
+                if destination_up(up_destinations, destination).await {
+                    if up_links[linkno as usize] {
+                        let reply = aux_transact(aux_mutex, linkno, &Packet::DestinationStatusRequest {
+                            destination: destination
+                        }, timer).await;
+                        match reply {
+                            Ok(Packet::DestinationDownReply) =>
+                                destination_set_up(routing_table, up_destinations, destination, false).await,
+                            Ok(Packet::DestinationOkReply) => (),
+                            Ok(Packet::DestinationSequenceErrorReply { channel }) =>
+                                error!("[DEST#{}] RTIO sequence error involving channel 0x{:04x}", destination, channel),
+                            Ok(Packet::DestinationCollisionReply { channel }) =>
+                                error!("[DEST#{}] RTIO collision involving channel 0x{:04x}", destination, channel),
+                            Ok(Packet::DestinationBusyReply { channel }) =>
+                                error!("[DEST#{}] RTIO busy error involving channel 0x{:04x}", destination, channel),
+                            Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
+                            Err(e) => error!("[DEST#{}] communication failed ({})", destination, e)
+                        }
+                    } else {
+                        destination_set_up(routing_table, up_destinations, destination, false).await;
+                    }
+                } else {
+                    if up_links[linkno as usize] {
+                        let reply = aux_transact(aux_mutex, linkno, &Packet::DestinationStatusRequest {
+                            destination: destination
+                        }, timer).await;
+                        match reply {
+                            Ok(Packet::DestinationDownReply) => (),
+                            Ok(Packet::DestinationOkReply) => {
+                                destination_set_up(routing_table, up_destinations, destination, true).await;
+                                init_buffer_space(destination as u8, linkno).await;
+                            },
+                            Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
+                            Err(e) => error!("[DEST#{}] communication failed ({})", destination, e)
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    pub async fn link_thread(aux_mutex: &Rc<Mutex<bool>>,
+            routing_table: &drtio_routing::RoutingTable,
+            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+            timer: GlobalTimer) {
+        let mut up_links = [false; csr::DRTIO.len()];
+        loop {
+            for linkno in 0..csr::DRTIO.len() {
+                let linkno = linkno as u8;
+                if up_links[linkno as usize] {
+                    /* link was previously up */
+                    if link_rx_up(linkno).await {
+                        process_unsolicited_aux(aux_mutex, linkno).await;
+                        process_local_errors(linkno).await;
+                    } else {
+                        info!("[LINK#{}] link is down", linkno);
+                        up_links[linkno as usize] = false;
+                    }
+                } else {
+                    /* link was previously down */
+                    if link_rx_up(linkno).await {
+                        info!("[LINK#{}] link RX became up, pinging", linkno);
+                        let ping_count = ping_remote(aux_mutex, linkno, timer).await;
+                        if ping_count > 0 {
+                            info!("[LINK#{}] remote replied after {} packets", linkno, ping_count);
+                            up_links[linkno as usize] = true;
+                            if let Err(e) = sync_tsc(aux_mutex, linkno, timer).await {
+                                error!("[LINK#{}] failed to sync TSC ({})", linkno, e);
+                            }
+                            if let Err(e) = load_routing_table(aux_mutex, linkno, routing_table, timer).await {
+                                error!("[LINK#{}] failed to load routing table ({})", linkno, e);
+                            }
+                            if let Err(e) = set_rank(aux_mutex, linkno, 1 as u8, timer).await {
+                                error!("[LINK#{}] failed to set rank ({})", linkno, e);
+                            }
+                            info!("[LINK#{}] link initialization completed", linkno);
+                        } else {
+                            error!("[LINK#{}] ping failed", linkno);
+                        }
+                    }
+                }
+            }
+            destination_survey(aux_mutex, routing_table, &up_links, up_destinations, timer).await;
+            let mut countdown = timer.countdown();
+            delay(&mut countdown, Milliseconds(200)).await;
+        }
+    }
+
+    #[allow(dead_code)]
+    pub fn reset(aux_mutex: Rc<Mutex<bool>>, mut timer: GlobalTimer) {
+        for linkno in 0..csr::DRTIO.len() {
+            unsafe {
+                (csr::DRTIO[linkno].reset_write)(1);
+            }
+        }
+        timer.delay_ms(1);
+        for linkno in 0..csr::DRTIO.len() {
+            unsafe {
+                (csr::DRTIO[linkno].reset_write)(0);
+            }
+        }
+
+        for linkno in 0..csr::DRTIO.len() {
+            let linkno = linkno as u8;
+            if task::block_on(link_rx_up(linkno)) {
+                let reply = task::block_on(aux_transact(&aux_mutex, linkno,
+                    &Packet::ResetRequest, timer));
+                match reply {
+                    Ok(Packet::ResetAck) => (),
+                    Ok(_) => error!("[LINK#{}] reset failed, received unexpected aux packet", linkno),
+                    Err(e) => error!("[LINK#{}] reset failed, aux packet error ({})", linkno, e)
+                }
+            }
+        }
+    }
+}
+
+#[cfg(not(has_drtio))]
+pub mod drtio {
+    use super::*;
+
+    pub fn startup(_aux_mutex: &Rc<Mutex<bool>>, _routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
+        _up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, _timer: GlobalTimer) {}
+    
+    #[allow(dead_code)]
+    pub fn reset(_aux_mutex: Rc<Mutex<bool>>, mut _timer: GlobalTimer) {}
+}
+
+pub fn startup(aux_mutex: &Rc<Mutex<bool>>,
+        routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
+        up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, 
+        timer: GlobalTimer) {
+    drtio::startup(aux_mutex, routing_table, up_destinations, timer);
+    unsafe {
+        csr::rtio_core::reset_phy_write(1);
+    }
+}
+
+#[allow(dead_code)]
+pub fn reset(aux_mutex: Rc<Mutex<bool>>, timer: GlobalTimer) {
+    unsafe {
+        csr::rtio_core::reset_write(1);
+    }
+    drtio::reset(aux_mutex, timer)
+}
--- a/src/satman/Cargo.toml
+++ b/src/satman/Cargo.toml
@ -0,0 +1,28 @@
+[package]
+authors = ["M-Labs"]
+name = "satman"
+version = "0.0.0"
+build = "build.rs"
+
+[features]
+target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
+target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
+default = ["target_zc706", ]
+
+[build-dependencies]
+build_zynq = { path = "../libbuild_zynq" }
+
+[dependencies]
+log = { version = "0.4", default-features = false }
+embedded-hal = "0.2"
+
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
+libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"] }
+
+libboard_artiq = { path = "../libboard_artiq" }
+unwind = { path = "../libunwind" }
+libc = { path = "../libc" }
--- a/src/satman/build.rs
+++ b/src/satman/build.rs
@ -0,0 +1,21 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+extern crate build_zynq;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("link.x"))
+        .unwrap()
+        .write_all(include_bytes!("link.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when link.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=link.x");
+    build_zynq::cfg();
+}
--- a/src/satman/link.x
+++ b/src/satman/link.x
@ -0,0 +1,86 @@
+ENTRY(Reset);
+
+MEMORY
+{
+    SDRAM : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
+}
+
+SECTIONS
+{
+    __text_start = .;
+    .text :
+    {
+        KEEP(*(.text.exceptions));
+        *(.text.boot);
+        *(.text .text.*);
+    } > SDRAM
+    __text_end = .;
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > SDRAM
+    __exidx_end = .;
+
+    .ARM.extab :
+    {
+        * (.ARM.extab*)
+    } > SDRAM
+ 
+    .rodata : ALIGN(4)
+    {
+        *(.rodata .rodata.*);
+    } > SDRAM
+ 
+    .data : ALIGN(4)
+    {
+        *(.data .data.*);
+    } > SDRAM
+ 
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        __bss_start = .;
+        *(.bss .bss.*);
+        . = ALIGN(4);
+        __bss_end = .;
+    } > SDRAM
+
+    .heap (NOLOAD) : ALIGN(8)
+    {
+        __heap0_start = .;
+        . += 0x8000000;
+        __heap0_end = .;
+        __heap1_start = .;
+        . += 0x8000000;
+        __heap1_end = .;
+    } > SDRAM
+
+    .stack1 (NOLOAD) : ALIGN(8)
+    {
+        __stack1_end = .;
+        . += 0x1000000;
+        __stack1_start = .;
+    } > SDRAM
+
+    .stack0 (NOLOAD) : ALIGN(8)
+    {
+        __stack0_end = .;
+        . += 0x20000;
+        __stack0_start = .;
+    } > SDRAM
+
+    .irq_stack1 (NOLOAD) : ALIGN(8)
+    {
+        __irq_stack1_end = .;
+        . += 0x100;
+        __irq_stack1_start = .;
+    } > SDRAM
+
+    .irq_stack0 (NOLOAD) : ALIGN(8)
+    {
+        __irq_stack0_end = .;
+        . += 0x100;
+        __irq_stack0_start = .;
+    } > SDRAM
+}
--- a/src/satman/satman.ld
+++ b/src/satman/satman.ld
@ -0,0 +1,55 @@
+INCLUDE generated/output_format.ld
+INCLUDE generated/regions.ld
+ENTRY(_reset_handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        *(.vectors)
+    } > main_ram
+
+    .text :
+    {
+        *(.text .text.*)
+    } > main_ram
+
+    /* https://sourceware.org/bugzilla/show_bug.cgi?id=20475 */
+    .got :
+    {
+        PROVIDE(_GLOBAL_OFFSET_TABLE_ = .);
+        *(.got)
+    } > main_ram
+
+    .got.plt :
+    {
+        *(.got.plt)
+    } > main_ram
+
+    .rodata :
+    {
+        _frodata = .;
+        *(.rodata .rodata.*)
+        _erodata = .;
+    } > main_ram
+
+    .data :
+    {
+        *(.data .data.*)
+    } > main_ram
+
+    .bss ALIGN(4) :
+    {
+        _fbss = .;
+        *(.bss .bss.*)
+        . = ALIGN(4);
+        _ebss = .;
+    } > main_ram
+
+    .stack :
+    {
+        _estack = .;
+        . += 0x10000;
+        _fstack = . - 4;
+    } > main_ram
+}
--- a/src/satman/src/jdac_common.rs
+++ b/src/satman/src/jdac_common.rs
@ -0,0 +1,37 @@
+pub const INIT: u8              = 0x00;
+pub const PRINT_STATUS: u8      = 0x01;
+pub const PRBS: u8              = 0x02;
+pub const STPL: u8              = 0x03;
+
+pub const SYSREF_DELAY_DAC: u8  = 0x10;
+pub const SYSREF_SLIP: u8       = 0x11;
+pub const SYNC: u8              = 0x12;
+
+pub const DDMTD_SYSREF_RAW: u8  = 0x20;
+pub const DDMTD_SYSREF: u8      = 0x21;
+
+
+fn average_2phases(a: i32, b: i32, modulo: i32) -> i32 {
+    let diff = ((a - b + modulo/2 + modulo) % modulo) - modulo/2;
+    return (modulo + b + diff/2) % modulo;
+}
+
+pub fn average_phases(phases: &[i32], modulo: i32) -> i32 {
+    if phases.len() == 1 {
+        panic!("input array length must be a power of 2");
+    } else if phases.len() == 2 {
+        average_2phases(phases[0], phases[1], modulo)
+    } else {
+        let cut = phases.len()/2;
+        average_2phases(
+            average_phases(&phases[..cut], modulo),
+            average_phases(&phases[cut..], modulo),
+            modulo)
+    }
+}
+
+pub const RAW_DDMTD_N_SHIFT: i32 = 6;
+pub const RAW_DDMTD_N: i32 = 1 << RAW_DDMTD_N_SHIFT;
+pub const DDMTD_DITHER_BITS: i32 = 1;
+pub const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS;
+pub const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
--- a/src/satman/src/main.rs
+++ b/src/satman/src/main.rs
@ -0,0 +1,634 @@
+#![no_std]
+#![no_main]
+#![feature(never_type, panic_info_message, asm, naked_functions)]
+#![feature(alloc_error_handler)]
+
+#[macro_use]
+extern crate log;
+
+extern crate embedded_hal;
+
+extern crate libboard_zynq;
+extern crate libboard_artiq;
+extern crate libsupport_zynq;
+extern crate libcortex_a9;
+extern crate libregister;
+
+extern crate unwind;
+
+extern crate alloc;
+
+use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
+use libsupport_zynq::ram;
+#[cfg(has_si5324)]
+use libboard_artiq::si5324;
+use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware};
+use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
+use libregister::{RegisterW, RegisterR};
+
+use embedded_hal::blocking::delay::DelayUs;
+use core::sync::atomic::{AtomicBool, Ordering};
+
+mod repeater;
+
+fn drtiosat_reset(reset: bool) {
+    unsafe {
+        csr::drtiosat::reset_write(if reset { 1 } else { 0 });
+    }
+}
+
+fn drtiosat_reset_phy(reset: bool) {
+    unsafe {
+        csr::drtiosat::reset_phy_write(if reset { 1 } else { 0 });
+    }
+}
+
+fn drtiosat_link_rx_up() -> bool {
+    unsafe {
+        csr::drtiosat::rx_up_read() == 1
+    }
+}
+
+fn drtiosat_tsc_loaded() -> bool {
+    unsafe {
+        let tsc_loaded = csr::drtiosat::tsc_loaded_read() == 1;
+        if tsc_loaded {
+            csr::drtiosat::tsc_loaded_write(1);
+        }
+        tsc_loaded
+    }
+}
+
+
+#[cfg(has_drtio_routing)]
+macro_rules! forward {
+    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {{
+        let hop = $routing_table.0[$destination as usize][$rank as usize];
+        if hop != 0 {
+            let repno = (hop - 1) as usize;
+            if repno < $repeaters.len() {
+                return $repeaters[repno].aux_forward($packet, $timer);
+            } else {
+                return Err(drtioaux::Error::RoutingError);
+            }
+        }
+    }}
+}
+
+#[cfg(not(has_drtio_routing))]
+macro_rules! forward {
+    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {}
+}
+
+fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
+        _routing_table: &mut drtio_routing::RoutingTable, _rank: &mut u8,
+        packet: drtioaux::Packet, timer: &mut GlobalTimer, i2c: &mut I2c) -> Result<(), drtioaux::Error> {
+    // In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
+    // and u16 otherwise; hence the `as _` conversion.
+    match packet {
+        drtioaux::Packet::EchoRequest =>
+            drtioaux::send(0, &drtioaux::Packet::EchoReply),
+        drtioaux::Packet::ResetRequest => {
+            info!("resetting RTIO");
+            drtiosat_reset(true);
+            timer.delay_us(100);
+            drtiosat_reset(false);
+            for rep in _repeaters.iter() {
+                if let Err(e) = rep.rtio_reset(timer) {
+                    error!("failed to issue RTIO reset ({:?})", e);
+                }
+            }
+            drtioaux::send(0, &drtioaux::Packet::ResetAck)
+        },
+
+        drtioaux::Packet::DestinationStatusRequest { destination: _destination } => {
+            #[cfg(has_drtio_routing)]
+            let hop = _routing_table.0[_destination as usize][*_rank as usize];
+            #[cfg(not(has_drtio_routing))]
+            let hop = 0;
+
+            if hop == 0 {
+                let errors;
+                unsafe {
+                    errors = csr::drtiosat::rtio_error_read();
+                }
+                if errors & 1 != 0 {
+                    let channel;
+                    unsafe {
+                        channel = csr::drtiosat::sequence_error_channel_read();
+                        csr::drtiosat::rtio_error_write(1);
+                    }
+                    drtioaux::send(0,
+                        &drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
+                } else if errors & 2 != 0 {
+                    let channel;
+                    unsafe {
+                        channel = csr::drtiosat::collision_channel_read();
+                        csr::drtiosat::rtio_error_write(2);
+                    }
+                    drtioaux::send(0,
+                        &drtioaux::Packet::DestinationCollisionReply { channel })?;
+                } else if errors & 4 != 0 {
+                    let channel;
+                    unsafe {
+                        channel = csr::drtiosat::busy_channel_read();
+                        csr::drtiosat::rtio_error_write(4);
+                    }
+                    drtioaux::send(0,
+                        &drtioaux::Packet::DestinationBusyReply { channel })?;
+                }
+                else {
+                    drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
+                }
+            }
+
+            #[cfg(has_drtio_routing)]
+            {
+                if hop != 0 {
+                    let hop = hop as usize;
+                    if hop <= csr::DRTIOREP.len() {
+                        let repno = hop - 1;
+                        match _repeaters[repno].aux_forward(&drtioaux::Packet::DestinationStatusRequest {
+                            destination: _destination
+                        }, timer) {
+                            Ok(()) => (),
+                            Err(drtioaux::Error::LinkDown) => drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?,
+                            Err(e) => {
+                                drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
+                                error!("aux error when handling destination status request: {:?}", e);
+                            },
+                        }
+                    } else {
+                        drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
+                    }
+                }
+            }
+
+            Ok(())
+        }
+
+        #[cfg(has_drtio_routing)]
+        drtioaux::Packet::RoutingSetPath { destination, hops } => {
+            _routing_table.0[destination as usize] = hops;
+            for rep in _repeaters.iter() {
+                if let Err(e) = rep.set_path(destination, &hops, timer) {
+                    error!("failed to set path ({:?})", e);
+                }
+            }
+            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
+        }
+        #[cfg(has_drtio_routing)]
+        drtioaux::Packet::RoutingSetRank { rank } => {
+            *_rank = rank;
+            drtio_routing::interconnect_enable_all(_routing_table, rank);
+
+            let rep_rank = rank + 1;
+            for rep in _repeaters.iter() {
+                if let Err(e) = rep.set_rank(rep_rank, timer) {
+                    error!("failed to set rank ({:?})", e);
+                }
+            }
+
+            info!("rank: {}", rank);
+            info!("routing table: {}", _routing_table);
+
+            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
+        }
+
+        #[cfg(not(has_drtio_routing))]
+        drtioaux::Packet::RoutingSetPath { destination: _, hops: _ } => {
+            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
+        }
+        #[cfg(not(has_drtio_routing))]
+        drtioaux::Packet::RoutingSetRank { rank: _ } => {
+            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
+        }
+
+        drtioaux::Packet::MonitorRequest { destination: _destination, channel: _channel, probe: _probe } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let value;
+            #[cfg(has_rtio_moninj)]
+            unsafe {
+                csr::rtio_moninj::mon_chan_sel_write(channel as _);
+                csr::rtio_moninj::mon_probe_sel_write(probe);
+                csr::rtio_moninj::mon_value_update_write(1);
+                value = csr::rtio_moninj::mon_value_read();
+            }
+            #[cfg(not(has_rtio_moninj))]
+            {
+                value = 0;
+            }
+            let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
+            drtioaux::send(0, &reply)
+        },
+        drtioaux::Packet::InjectionRequest { destination: _destination, channel: _channel, 
+                                             overrd: _overrd, value: _value } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            #[cfg(has_rtio_moninj)]
+            unsafe {
+                csr::rtio_moninj::inj_chan_sel_write(channel as _);
+                csr::rtio_moninj::inj_override_sel_write(overrd);
+                csr::rtio_moninj::inj_value_write(value);
+            }
+            Ok(())
+        },
+        drtioaux::Packet::InjectionStatusRequest { destination: _destination, 
+                                                   channel: _channel, overrd: _overrd } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let value;
+            #[cfg(has_rtio_moninj)]
+            unsafe {
+                csr::rtio_moninj::inj_chan_sel_write(channel as _);
+                csr::rtio_moninj::inj_override_sel_write(overrd);
+                value = csr::rtio_moninj::inj_value_read();
+            }
+            #[cfg(not(has_rtio_moninj))]
+            {
+                value = 0;
+            }
+            drtioaux::send(0, &drtioaux::Packet::InjectionStatusReply { value: value })
+        },
+
+        drtioaux::Packet::I2cStartRequest { destination: _destination, busno: _busno } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let succeeded = i2c.start().is_ok();
+            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+        }
+        drtioaux::Packet::I2cRestartRequest { destination: _destination, busno: _busno } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let succeeded = i2c.restart().is_ok();
+            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+        }
+        drtioaux::Packet::I2cStopRequest { destination: _destination, busno: _busno } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let succeeded = i2c.stop().is_ok();
+            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+        }
+        drtioaux::Packet::I2cWriteRequest { destination: _destination, busno: _busno, data } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            match i2c.write(data) {
+                Ok(ack) => drtioaux::send(0,
+                    &drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
+                Err(_) => drtioaux::send(0,
+                    &drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
+            }
+        }
+        drtioaux::Packet::I2cReadRequest { destination: _destination, busno: _busno, ack } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            match i2c.read(ack) {
+                Ok(data) => drtioaux::send(0,
+                    &drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
+                Err(_) => drtioaux::send(0,
+                    &drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
+            }
+        }
+
+        drtioaux::Packet::SpiSetConfigRequest { destination: _destination, busno: _busno, 
+                                                flags: _flags, length: _length, div: _div, cs: _cs } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            // todo: reimplement when/if SPI is available
+            //let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
+            drtioaux::send(0,
+                &drtioaux::Packet::SpiBasicReply { succeeded: false })
+        },
+        drtioaux::Packet::SpiWriteRequest { destination: _destination, busno: _busno, data: _data } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            // todo: reimplement when/if SPI is available
+            //let succeeded = spi::write(busno, data).is_ok();
+            drtioaux::send(0,
+                &drtioaux::Packet::SpiBasicReply { succeeded: false })
+        }
+        drtioaux::Packet::SpiReadRequest { destination: _destination, busno: _busno } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            // todo: reimplement when/if SPI is available
+            // match spi::read(busno) {
+            //     Ok(data) => drtioaux::send(0,
+            //         &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
+            //     Err(_) => drtioaux::send(0,
+            //         &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
+            // }
+            drtioaux::send(0,
+                &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
+        }
+
+        drtioaux::Packet::JdacBasicRequest { destination: _destination, dacno: _dacno,
+                                             reqno: _reqno, param: _param } => {
+            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
+            let (succeeded, retval) = (false, 0);
+            drtioaux::send(0,
+                &drtioaux::Packet::JdacBasicReply { succeeded: succeeded, retval: retval })
+        }
+
+        _ => {
+            warn!("received unexpected aux packet");
+            Ok(())
+        }
+    }
+}
+
+fn process_aux_packets(repeaters: &mut [repeater::Repeater],
+        routing_table: &mut drtio_routing::RoutingTable, rank: &mut u8, 
+        timer: &mut GlobalTimer, i2c: &mut I2c) {
+    let result =
+        drtioaux::recv(0).and_then(|packet| {
+            if let Some(packet) = packet {
+                process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c)
+            } else {
+                Ok(())
+            }
+        });
+    match result {
+        Ok(()) => (),
+        Err(e) => warn!("aux packet error ({:?})", e)
+    }
+}
+
+fn drtiosat_process_errors() {
+    let errors;
+    unsafe {
+        errors = csr::drtiosat::protocol_error_read();
+    }
+    if errors & 1 != 0 {
+        error!("received packet of an unknown type");
+    }
+    if errors & 2 != 0 {
+        error!("received truncated packet");
+    }
+    if errors & 4 != 0 {
+        let destination;
+        unsafe {
+            destination = csr::drtiosat::buffer_space_timeout_dest_read();
+        }
+        error!("timeout attempting to get buffer space from CRI, destination=0x{:02x}", destination)
+    }
+    if errors & 8 != 0 {
+        let channel;
+        let timestamp_event;
+        let timestamp_counter;
+        unsafe {
+            channel = csr::drtiosat::underflow_channel_read();
+            timestamp_event = csr::drtiosat::underflow_timestamp_event_read() as i64;
+            timestamp_counter = csr::drtiosat::underflow_timestamp_counter_read() as i64;
+        }
+        error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
+               channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
+    }
+    if errors & 16 != 0 {
+        error!("write overflow");
+    }
+    unsafe {
+        csr::drtiosat::protocol_error_write(errors);
+    }
+}
+
+
+#[cfg(has_rtio_crg)]
+fn init_rtio_crg(timer: GlobalTimer) {
+    unsafe {
+        csr::rtio_crg::pll_reset_write(0);
+    }
+    timer.delay_us(150);
+    let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
+    if !locked {
+        error!("RTIO clock failed");
+    }
+}
+
+#[cfg(not(has_rtio_crg))]
+fn init_rtio_crg(_timer: GlobalTimer) { }
+
+fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
+    let now = timer.get_time();
+    let mut ts_ms = Milliseconds(*ts);
+    if now > ts_ms {
+        ts_ms = now + Milliseconds(200);
+        *ts = ts_ms.0;
+    }
+}
+
+#[cfg(has_si5324)]
+const SI5324_SETTINGS: si5324::FrequencySettings
+    = si5324::FrequencySettings {
+    n1_hs  : 5,
+    nc1_ls : 8,
+    n2_hs  : 7,
+    n2_ls  : 360,
+    n31    : 63,
+    n32    : 63,
+    bwsel  : 4,
+    crystal_ref: true
+};
+
+static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
+
+#[no_mangle]
+pub extern fn main_core0() -> i32 {
+    enable_l2_cache(0x8);
+
+    let mut timer = GlobalTimer::start();
+
+    let buffer_logger = unsafe {
+        logger::BufferLogger::new(&mut LOG_BUFFER[..])
+    };
+    buffer_logger.set_uart_log_level(log::LevelFilter::Info);
+    buffer_logger.register();
+    log::set_max_level(log::LevelFilter::Info);
+    
+    init_gateware();
+
+    info!("ARTIQ satellite manager starting...");
+    info!("gateware ident {}", identifier_read(&mut [0; 64]));
+
+    ram::init_alloc_core0();
+
+    let mut i2c = I2c::i2c0();
+    i2c.init().expect("I2C initialization failed");
+
+    #[cfg(has_si5324)]
+    si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
+
+    unsafe {
+        csr::drtio_transceiver::stable_clkin_write(1);
+    }
+    timer.delay_us(1500); // wait for CPLL/QPLL lock
+
+    unsafe {
+        csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
+    }
+    init_rtio_crg(timer);
+
+    #[cfg(has_drtio_routing)]
+    let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
+    #[cfg(not(has_drtio_routing))]
+    let mut repeaters = [repeater::Repeater::default(); 0];
+    for i in 0..repeaters.len() {
+        repeaters[i] = repeater::Repeater::new(i as u8);
+    } 
+    let mut routing_table = drtio_routing::RoutingTable::default_empty();
+    let mut rank = 1;
+
+    let mut hardware_tick_ts = 0;
+
+    loop {
+        while !drtiosat_link_rx_up() {
+            drtiosat_process_errors();
+            #[allow(unused_mut)]
+            for mut rep in repeaters.iter_mut() {
+                rep.service(&routing_table, rank, &mut timer);
+            }
+            hardware_tick(&mut hardware_tick_ts, &mut timer);
+        }
+
+        info!("uplink is up, switching to recovered clock");
+        #[cfg(has_siphaser)]
+        {
+            si5324::siphaser::select_recovered_clock(&mut i2c, true, &mut timer).expect("failed to switch clocks");
+            si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
+        }
+
+        drtioaux::reset(0);
+        drtiosat_reset(false);
+        drtiosat_reset_phy(false);
+
+        while drtiosat_link_rx_up() {
+            drtiosat_process_errors();
+            process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c);
+            #[allow(unused_mut)]
+            for mut rep in repeaters.iter_mut() {
+                rep.service(&routing_table, rank, &mut timer);
+            }
+            hardware_tick(&mut hardware_tick_ts, &mut timer);
+            if drtiosat_tsc_loaded() {
+                info!("TSC loaded from uplink");
+                for rep in repeaters.iter() {
+                    if let Err(e) = rep.sync_tsc(&mut timer) {
+                        error!("failed to sync TSC ({:?})", e);
+                    }
+                }
+                if let Err(e) = drtioaux::send(0, &drtioaux::Packet::TSCAck) {
+                    error!("aux packet error: {:?}", e);
+                }
+            }
+        }
+
+        drtiosat_reset_phy(true);
+        drtiosat_reset(true);
+        drtiosat_tsc_loaded();
+        info!("uplink is down, switching to local oscillator clock");
+        #[cfg(has_siphaser)]
+        si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
+    }
+}
+
+extern "C" {
+    static mut __stack1_start: u32;
+}
+
+interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
+    if MPIDR.read().cpu_id() == 1{
+        let mpcore = mpcore::RegisterBlock::mpcore();
+        let mut gic = gic::InterruptController::gic(mpcore);
+        let id = gic.get_interrupt_id();
+        if id.0 == 0 {
+            gic.end_interrupt(id);
+            asm::exit_irq();
+            SP.write(&mut __stack1_start as *mut _ as u32);
+            asm::enable_irq();
+            CORE1_RESTART.store(false, Ordering::Relaxed);
+            notify_spin_lock();
+            main_core1();
+        }
+    stdio::drop_uart();
+    }
+    loop {}
+});
+
+static mut PANICKED: [bool; 2] = [false; 2];
+
+static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
+
+pub fn restart_core1() {
+    let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
+    CORE1_RESTART.store(true, Ordering::Relaxed);
+    interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
+    while CORE1_RESTART.load(Ordering::Relaxed) {
+        spin_lock_yield();
+    }
+}
+
+#[no_mangle]
+pub fn main_core1() {
+    let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
+    interrupt_controller.enable_interrupts();
+
+    loop {}
+}
+
+#[no_mangle]
+pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) {
+
+    fn hexdump(addr: u32) {
+        let addr = (addr - addr % 4) as *const u32;
+        let mut ptr  = addr;
+        println!("@ {:08p}", ptr);
+        for _ in 0..4 {
+            print!("+{:04x}: ", ptr as usize - addr as usize);
+            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
+            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
+            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
+            print!("{:08x}\n",  unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
+        }
+    }
+
+    hexdump(pc);
+    hexdump(ea);
+    panic!("exception at PC 0x{:x}, EA 0x{:x}", pc, ea)
+}
+
+#[no_mangle] // https://github.com/rust-lang/rust/issues/{38281,51647}
+#[panic_handler]
+pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
+    let id = MPIDR.read().cpu_id() as usize;
+    print!("Core {} ", id);
+    unsafe {
+        if PANICKED[id] {
+            println!("nested panic!");
+            loop {}
+        }
+        PANICKED[id] = true;
+    }
+    print!("panic at ");
+    if let Some(location) = info.location() {
+        print!("{}:{}:{}", location.file(), location.line(), location.column());
+    } else {
+        print!("unknown location");
+    }
+    if let Some(message) = info.message() {
+        println!(": {}", message);
+    } else {
+        println!("");
+    }
+
+
+    loop {}
+}
+
+// linker symbols
+extern "C" {
+    static __text_start: u32;
+    static __text_end: u32;
+    static __exidx_start: u32;
+    static __exidx_end: u32;
+}
+
+#[no_mangle]
+extern fn dl_unwind_find_exidx(_pc: *const u32, len_ptr: *mut u32) -> *const u32 {
+    let length;
+    let start: *const u32;
+    unsafe {
+        length = (&__exidx_end as *const u32).offset_from(&__exidx_start) as u32;
+        start = &__exidx_start;
+        *len_ptr = length;
+    }
+    start
+}
--- a/src/satman/src/repeater.rs
+++ b/src/satman/src/repeater.rs
@ -0,0 +1,290 @@
+use libboard_artiq::{drtioaux, drtio_routing};
+use libboard_zynq::timer::GlobalTimer;
+
+#[cfg(has_drtio_routing)]
+use libboard_artiq::{pl::csr};
+#[cfg(has_drtio_routing)]
+use libboard_zynq::time::Milliseconds;
+#[cfg(has_drtio_routing)]
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+
+#[cfg(has_drtio_routing)]
+fn rep_link_rx_up(repno: u8) -> bool {
+    let repno = repno as usize;
+    unsafe {
+        (csr::DRTIOREP[repno].rx_up_read)() == 1
+    }
+}
+
+#[cfg(has_drtio_routing)]
+#[derive(Clone, Copy, PartialEq)]
+enum RepeaterState {
+    Down,
+    SendPing { ping_count: u16 },
+    WaitPingReply { ping_count: u16, timeout: Milliseconds },
+    Up,
+    Failed
+}
+
+#[cfg(has_drtio_routing)]
+impl Default for RepeaterState {
+    fn default() -> RepeaterState { RepeaterState::Down }
+}
+
+#[cfg(has_drtio_routing)]
+#[derive(Clone, Copy, Default)]
+pub struct Repeater {
+    repno: u8,
+    auxno: u8,
+    state: RepeaterState
+}
+
+#[cfg(has_drtio_routing)]
+impl Repeater {
+    pub fn new(repno: u8) -> Repeater {
+        Repeater {
+            repno: repno,
+            auxno: repno + 1,
+            state: RepeaterState::Down
+        }
+    }
+
+    #[allow(dead_code)]
+    pub fn is_up(&self) -> bool {
+        self.state == RepeaterState::Up
+    }
+
+    pub fn service(&mut self, routing_table: &drtio_routing::RoutingTable, rank: u8,
+        timer: &mut GlobalTimer) {
+        self.process_local_errors();
+
+        match self.state {
+            RepeaterState::Down => {
+                if rep_link_rx_up(self.repno) {
+                    info!("[REP#{}] link RX became up, pinging", self.repno);
+                    self.state = RepeaterState::SendPing { ping_count: 0 };
+                }
+            }
+            RepeaterState::SendPing { ping_count } => {
+                if rep_link_rx_up(self.repno) {
+                    drtioaux::send(self.auxno, &drtioaux::Packet::EchoRequest).unwrap();
+                    self.state = RepeaterState::WaitPingReply {
+                        ping_count: ping_count + 1,
+                        timeout: timer.get_time() + Milliseconds(100)
+                    }
+                } else {
+                    error!("[REP#{}] link RX went down during ping", self.repno);
+                    self.state = RepeaterState::Down;
+                }
+            }
+            RepeaterState::WaitPingReply { ping_count, timeout } => {
+                if rep_link_rx_up(self.repno) {
+                    if let Ok(Some(drtioaux::Packet::EchoReply)) = drtioaux::recv(self.auxno) {
+                        info!("[REP#{}] remote replied after {} packets", self.repno, ping_count);
+                        self.state = RepeaterState::Up;
+                        if let Err(e) = self.sync_tsc(timer) {
+                            error!("[REP#{}] failed to sync TSC ({:?})", self.repno, e);
+                            self.state = RepeaterState::Failed;
+                            return;
+                        }
+                        if let Err(e) = self.load_routing_table(routing_table, timer) {
+                            error!("[REP#{}] failed to load routing table ({:?})", self.repno, e);
+                            self.state = RepeaterState::Failed;
+                            return;
+                        }
+                        if let Err(e) = self.set_rank(rank + 1, timer) {
+                            error!("[REP#{}] failed to set rank ({:?})", self.repno, e);
+                            self.state = RepeaterState::Failed;
+                            return;
+                        }
+                    } else {
+                        if timer.get_time() > timeout {
+                            if ping_count > 200 {
+                                error!("[REP#{}] ping failed", self.repno);
+                                self.state = RepeaterState::Failed;
+                            } else {
+                                self.state = RepeaterState::SendPing { ping_count: ping_count };
+                            }
+                        }
+                    }
+                } else {
+                    error!("[REP#{}] link RX went down during ping", self.repno);
+                    self.state = RepeaterState::Down;
+                }
+            }
+            RepeaterState::Up => {
+                self.process_unsolicited_aux();
+                if !rep_link_rx_up(self.repno) {
+                    info!("[REP#{}] link is down", self.repno);
+                    self.state = RepeaterState::Down;
+                }
+            }
+            RepeaterState::Failed => {
+                if !rep_link_rx_up(self.repno) {
+                    info!("[REP#{}] link is down", self.repno);
+                    self.state = RepeaterState::Down;
+                }
+            }
+        }
+    }
+
+    fn process_unsolicited_aux(&self) {
+        match drtioaux::recv(self.auxno) {
+            Ok(Some(packet)) => warn!("[REP#{}] unsolicited aux packet: {:?}", self.repno, packet),
+            Ok(None) => (),
+            Err(_) => warn!("[REP#{}] aux packet error", self.repno)
+        }
+    }
+
+    fn process_local_errors(&self) {
+        let repno = self.repno as usize;
+        let errors;
+        unsafe {
+            errors = (csr::DRTIOREP[repno].protocol_error_read)();
+        }
+        if errors & 1 != 0 {
+            error!("[REP#{}] received packet of an unknown type", repno);
+        }
+        if errors & 2 != 0 {
+            error!("[REP#{}] received truncated packet", repno);
+        }
+        if errors & 4 != 0 {
+            let cmd;
+            let chan_sel;
+            unsafe {
+                cmd = (csr::DRTIOREP[repno].command_missed_cmd_read)();
+                chan_sel = (csr::DRTIOREP[repno].command_missed_chan_sel_read)();
+            }
+            error!("[REP#{}] CRI command missed, cmd={}, chan_sel=0x{:06x}", repno, cmd, chan_sel)
+        }
+        if errors & 8 != 0 {
+            let destination;
+            unsafe {
+                destination = (csr::DRTIOREP[repno].buffer_space_timeout_dest_read)();
+            }
+            error!("[REP#{}] timeout attempting to get remote buffer space, destination=0x{:02x}", repno, destination);
+        }
+        unsafe {
+            (csr::DRTIOREP[repno].protocol_error_write)(errors);
+        }
+    }
+
+    fn recv_aux_timeout(&self, timeout: u32, timer: &mut GlobalTimer) -> Result<drtioaux::Packet, drtioaux::Error> {
+        let max_time = timer.get_time() + Milliseconds(timeout.into());
+        loop {
+            if !rep_link_rx_up(self.repno) {
+                return Err(drtioaux::Error::LinkDown);
+            }
+            if timer.get_time() > max_time {
+                return Err(drtioaux::Error::TimedOut);
+            }
+            match drtioaux::recv(self.auxno) {
+                Ok(Some(packet)) => return Ok(packet),
+                Ok(None) => (),
+                Err(e) => return Err(e)
+            }
+        }
+    }
+
+    pub fn aux_forward(&self, request: &drtioaux::Packet, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        if self.state != RepeaterState::Up {
+            return Err(drtioaux::Error::LinkDown);
+        }
+        drtioaux::send(self.auxno, request).unwrap();
+        let reply = self.recv_aux_timeout(200, timer)?;
+        drtioaux::send(0, &reply).unwrap();
+        Ok(())
+    }
+
+    pub fn sync_tsc(&self, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        if self.state != RepeaterState::Up {
+            return Ok(());
+        }
+
+        let repno = self.repno as usize;
+        unsafe {
+            (csr::DRTIOREP[repno].set_time_write)(1);
+            while (csr::DRTIOREP[repno].set_time_read)() == 1 {}
+        }
+
+        // TSCAck is the only aux packet that is sent spontaneously
+        // by the satellite, in response to a TSC set on the RT link.
+        let reply = self.recv_aux_timeout(10000, timer)?;
+        if reply == drtioaux::Packet::TSCAck {
+            return Ok(());
+        } else {
+            return Err(drtioaux::Error::UnexpectedReply);
+        }
+    }
+
+    pub fn set_path(&self, destination: u8, hops: &[u8; drtio_routing::MAX_HOPS], timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        if self.state != RepeaterState::Up {
+            return Ok(());
+        }
+
+        drtioaux::send(self.auxno, &drtioaux::Packet::RoutingSetPath {
+            destination: destination,
+            hops: *hops
+        }).unwrap();
+        let reply = self.recv_aux_timeout(200, timer)?;
+        if reply != drtioaux::Packet::RoutingAck {
+            return Err(drtioaux::Error::UnexpectedReply);
+        }
+        Ok(())
+    }
+
+    pub fn load_routing_table(&self, routing_table: &drtio_routing::RoutingTable, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        for i in 0..drtio_routing::DEST_COUNT {
+            self.set_path(i as u8, &routing_table.0[i], timer)?;
+        }
+        Ok(())
+    }
+
+    pub fn set_rank(&self, rank: u8, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        if self.state != RepeaterState::Up {
+            return Ok(());
+        }
+        drtioaux::send(self.auxno, &drtioaux::Packet::RoutingSetRank {
+            rank: rank
+        }).unwrap();
+        let reply = self.recv_aux_timeout(200, timer)?;
+        if reply != drtioaux::Packet::RoutingAck {
+            return Err(drtioaux::Error::UnexpectedReply);
+        }
+        Ok(())
+    }
+
+    pub fn rtio_reset(&self, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+        let repno = self.repno as usize;
+        unsafe { (csr::DRTIOREP[repno].reset_write)(1); }
+        timer.delay_us(100);
+        unsafe { (csr::DRTIOREP[repno].reset_write)(0); }
+
+        if self.state != RepeaterState::Up {
+            return Ok(());
+        }
+
+        drtioaux::send(self.auxno, &drtioaux::Packet::ResetRequest).unwrap();
+        let reply = self.recv_aux_timeout(200, timer)?;
+        if reply != drtioaux::Packet::ResetAck {
+            return Err(drtioaux::Error::UnexpectedReply);
+        }
+        Ok(())
+    }
+}
+
+#[cfg(not(has_drtio_routing))]
+#[derive(Clone, Copy, Default)]
+pub struct Repeater {
+}
+
+#[cfg(not(has_drtio_routing))]
+impl Repeater {
+    pub fn new(_repno: u8) -> Repeater { Repeater::default() }
+
+    pub fn service(&self, _routing_table: &drtio_routing::RoutingTable, _rank: u8, _timer: &mut GlobalTimer) { }
+
+    pub fn sync_tsc(&self, _timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> { Ok(()) }
+
+    pub fn rtio_reset(&self, _timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> { Ok(()) }
+}
Author	SHA1	Message	Date
mwojcik	ad7d488d42	make: change main target names to avoid collision	2021-10-05 11:55:45 +02:00
mwojcik	74e4f8dc5f	makefile: target names match target files	2021-10-05 10:53:58 +02:00
mwojcik	d57cceb494	added different fw type support for local_run	2021-10-05 10:04:14 +02:00
mwojcik	c3491ed6cd	Merge branch 'master' into drtio_port	2021-10-04 12:52:53 +02:00
mwojcik	db1c9d336e	aux_controller: fix class parent	2021-10-04 08:53:38 +02:00
mwojcik	b9da4c27fe	one more unnecessary comment gone	2021-10-01 15:37:00 +02:00
mwojcik	38088cea87	cleanup, less unnecessary comments and dup code	2021-10-01 15:35:00 +02:00
mwojcik	26483e852c	libboard_artiq: fixes for siphaser, cleanup	2021-10-01 15:08:00 +02:00
mwojcik	758adf0495	drtioaux: created async version	2021-10-01 12:53:31 +02:00
mwojcik	2caa48f24b	libboard_artiq: changed edition to 2018 for async	2021-10-01 11:49:55 +02:00
mwojcik	5f06db8787	drtio: swap byte order, add work buffer, comm ok	2021-09-30 13:32:19 +02:00
mwojcik	f23c6cdb18	aux_controller: fix axi sram data paths	2021-09-29 14:01:06 +02:00
mwojcik	8ab2b3f299	aux_controller: connect r/w/b lanes to axi bus	2021-09-29 11:50:52 +02:00
mwojcik	b9f0bb3899	runtime: enable target feature for libboard_artiq	2021-09-27 15:50:20 +02:00
mwojcik	f897c41d2b	master: fix lifetime of drtio variables	2021-09-27 15:06:32 +02:00
mwojcik	6dbd817d3e	master: runtime fixes per compiler's requests	2021-09-24 14:15:33 +02:00
mwojcik	94ecc48d5d	master: fix typos, missing imports	2021-09-24 11:34:57 +02:00
mwojcik	32df88c771	runtime: async delay instead of usual	2021-09-24 09:49:49 +02:00
mwojcik	45b9d50e70	gateware: fixed zc706/kasli-soc master typos	2021-09-23 14:54:49 +02:00
mwojcik	bb5af4f156	gateware: fixing up master classes	2021-09-23 14:22:30 +02:00
mwojcik	e8541c4cf5	runtime: moving rtio_mgt to async/await	2021-09-23 13:22:27 +02:00
mwojcik	f1b22330d3	runtime: rtio_mgt's async_error_read exists already	2021-09-21 12:02:27 +02:00
mwojcik	85e7784b91	runtime: restored refcells for rtio_mgt	2021-09-21 11:48:59 +02:00
mwojcik	da366b7a0d	runtime: added drtio init function	2021-09-21 11:13:36 +02:00
mwojcik	589c4bebe4	master: moninj supports local and remote with dispatch	2021-09-20 15:25:55 +02:00
mwojcik	241113c6b2	'while' is reverse of 'until'...	2021-09-20 15:03:49 +02:00
mwojcik	414cfd2fa7	* few cleanups * libcortexa9 mutex behavior understood * io.until replaced with spinlock	2021-09-20 14:41:15 +02:00
mwojcik	ff77204d37	moving drtio master code from mainline artiq: moninj and rtio_mgt	2021-09-17 14:20:37 +02:00
mwojcik	0b89cf8002	slight cleanup, started work on master mode	2021-09-16 15:38:51 +02:00
mwojcik	1160676fd6	zc706: changed io standard for si5324 on nist backplates	2021-09-15 11:19:43 +02:00
mwojcik	176e370872	kasli_soc satellite: fixed rust config si5324: fixed double mut borrow in soft reset	2021-09-13 15:36:47 +02:00
mwojcik	9c09216281	updated gateware for not yet published migen-axi changes	2021-09-13 15:06:34 +02:00
mwojcik	d3152f3d24	changed auxctrl tx/rx memory to axi2csr_sram	2021-09-10 15:25:05 +02:00
mwojcik	9c14694fc4	added rtioclockmultiplier where applicable (nist variants don't compile for other reasons now)	2021-09-07 15:22:01 +02:00
mwojcik	1bddad6ff2	kasli_soc: fixes to make satellite variant work	2021-09-07 14:51:46 +02:00
mwojcik	cd3e46fb3a	fixes in makefile for kasli and satellite variants	2021-09-06 15:23:53 +02:00
mwojcik	76929d2aa1	zc706: * broke down platforms (refactor), * added nist master/sat variants * master doesn't build yet, satellite only simple variant	2021-09-06 14:30:09 +02:00
mwojcik	20681a13c4	gateware: fixed cfg keys - case consistent w/ code	2021-09-06 10:57:42 +02:00
mwojcik	5e916f588e	libboard_zynq: * pca9548 selection for si5234 * added proper support for targets satman: * removed unnecessary messages * added libboard_zynq to targets in cargo.toml	2021-09-06 10:44:25 +02:00
mwojcik	9022064cf1	added siphaser to zc706 satellite, small fixes	2021-09-06 09:06:16 +02:00
mwojcik	b678408105	rustc_cfg is case sensitive. Si5324 was not achnowledged.	2021-09-03 14:58:17 +02:00
mwojcik	0c259d9833	kasli_soc: satellite brought to the same level as zc706	2021-09-03 11:05:41 +02:00
mwojcik	3840ebaf74	better solution for fw type based on variant	2021-09-02 15:02:15 +02:00
mwojcik	e38c4a14ca	code cleanup: * moved shared init_gateware to libboard_artiq * suppressed warnings for zc706 satman	2021-09-02 14:39:34 +02:00
mwojcik	d19a30a2d9	satman: init gateware, set log level	2021-09-02 12:50:42 +02:00
mwojcik	7d719d07e9	default.nix: added symlink for satman fw	2021-09-02 12:50:20 +02:00
mwojcik	cdb58af5b3	remote_run: support loading other firmware types	2021-09-02 12:49:35 +02:00
mwojcik	67f4ec5782	satman: satisfied libunwind's demands, compiles	2021-09-01 15:05:08 +02:00
mwojcik	1ad0e77cae	satman: added unwind as it seems necessary	2021-09-01 11:42:41 +02:00
mwojcik	5cfcee6d20	satman: not a library - made closer to runtime	2021-09-01 11:05:46 +02:00
mwojcik	37e8b576b1	satellite: * fixing repeaters that can't exist on zc706 * fixing various warnings * fixed timer and i2c references	2021-08-31 15:25:56 +02:00
mwojcik	36bf30c446	satman: removed irrelevant (kasli v2) code	2021-08-31 13:47:43 +02:00
mwojcik	e56f99b3ae	satman: straightened up drtio interface	2021-08-31 12:46:52 +02:00
mwojcik	f80f2ac99d	added support for satellite variants in nix-build	2021-08-31 11:55:34 +02:00
mwojcik	db9b744825	satman: fixed timeout millisecond/u64 mismatch	2021-08-30 15:06:46 +02:00
mwojcik	be0baf5da8	satman: adjusted drtio::Error instances	2021-08-30 14:38:00 +02:00
mwojcik	59cf4bc689	libboard_zynq: fully modified to work with core_io	2021-08-27 15:16:13 +02:00
mwojcik	581f6c6b4e	libboard_artiq: tried moving drtio to io::proto	2021-08-27 14:44:54 +02:00
mwojcik	e0516eeda9	libio: removed custom read/write, moved to core_io	2021-08-27 13:12:19 +02:00
mwojcik	9b2b1dadaa	satman: repeater fixes, missing code	2021-08-26 15:20:33 +02:00
mwojcik	cb3f0a404c	libio: read/write traits from libio not core_io	2021-08-26 14:59:04 +02:00
mwojcik	10cbea72a2	clean up in dependencies	2021-08-26 13:16:51 +02:00
mwojcik	ff7ba56d26	forgot to remove a debug print	2021-08-26 12:54:19 +02:00
mwojcik	39d522e1a7	drtioaux_proto: removed failure, need to fix traits	2021-08-25 13:03:54 +02:00
mwojcik	a8a2da575b	libboard_artiq: added mem.rs, yet to fix drtioaux	2021-08-24 14:11:30 +02:00
mwojcik	37eb4669fb	makefile: satman support, separated from runtime	2021-08-24 13:57:10 +02:00
mwojcik	b585eaaa37	zc706: added memory iface generator	2021-08-24 13:51:38 +02:00
mwojcik	1358c8bfe9	zc706 gateware: base class for drtio is SoCCore	2021-08-24 12:01:04 +02:00
mwojcik	b2d9003d9f	drtioaucontroller: made two decoders	2021-08-20 15:13:56 +02:00
mwojcik	e43684a3ed	moved AXI SRAM to migen-axi	2021-08-18 12:36:17 +02:00
mwojcik	7b868e1c9d	few fixes, typos and missed unnecessary statements	2021-08-17 13:16:02 +02:00
mwojcik	61f81cec47	sram: redesigned write FSM. removed unused signals	2021-08-17 11:10:08 +02:00
mwojcik	3e1d14ff38	replaced increment logic with ready Incr module	2021-08-16 15:33:50 +02:00
mwojcik	67ed7fae78	sram: or operator in wrong place for wrapped burst	2021-08-16 12:05:23 +02:00
mwojcik	f015d6732b	sram: support for different burst settings on read	2021-08-16 11:51:50 +02:00
mwojcik	b6dd5bea68	sram: fixed wrong assumptions on some signals	2021-08-13 14:58:18 +02:00
mwojcik	bfe0c34f57	sram: rewrote read fsm for sram	2021-08-13 14:14:43 +02:00
mwojcik	39509f01d6	aux_controller: sram ported to axi, first attempt	2021-08-13 13:06:10 +02:00
mwojcik	066987bf07	aux_controller: started porting from wb to axi	2021-08-11 14:34:44 +02:00
mwojcik	7ff59f57a9	gateware: updated gtx interface	2021-08-10 15:11:21 +02:00
mwojcik	118893c0b2	disabled adding axi slave/mem drtioauxcontroller uses AXI rather than Wishbone still won't compile - unresolved clock domain error	2021-08-06 15:25:59 +02:00
mwojcik	ae86bbb76e	zc706 gateware fixes: replaced crg cd_sys.clk with ps7.cd_sys.clk restored gpio removed mentions of i2c user_sma_clock consumed by _RTIOCRG already	2021-08-06 13:31:16 +02:00
mwojcik	d68cf7dd49	gateware: replaced wb slave w/ axi (diff soccore)	2021-08-06 11:05:49 +02:00
mwojcik	f9860a61b7	sys_clk_freq is actually 125mhz	2021-08-06 10:39:37 +02:00
mwojcik	d1705113aa	kasli: gtx transcvr expects separate tx/rx pads	2021-08-06 10:05:45 +02:00
mwojcik	97dfa07bdb	determined probable sys_clk_freq for GTX transcvr	2021-08-06 10:05:04 +02:00
mwojcik	f45fa28dac	satman: * added Zynq-specific impls of basic functions (main/panic/irq) * added makefile definition * fixed drtioaux compilation error (feature never_type)	2021-08-05 16:05:44 +02:00
mwojcik	ecc8a0ccc0	kasli-soc: qpll is not part of this board, removed mentions	2021-08-04 16:44:08 +02:00
mwojcik	e17b398483	added siphaser driver code for drtio satellites	2021-08-04 12:55:03 +02:00
mwojcik	b95692548e	Merge branch 'master' into drtio_port	2021-08-04 09:38:08 +02:00
mwojcik	98b3b74bc2	added kasli-soc variants based on demo	2021-08-03 11:54:44 +02:00
mwojcik	6a9729bede	Merge branch 'master' into drtio_port	2021-08-03 09:56:14 +02:00
mwojcik	b2dd68bd92	removed unnecessary and wrong add_drtio	2021-08-03 09:52:50 +02:00
mwojcik	cafbe97e47	zc706: added targets to default.nix, fixed wrong base cls	2021-07-30 15:14:40 +02:00
mwojcik	3ba7fe1e6b	kasli_soc uses gtx transceiver instead of gtp	2021-07-30 12:52:58 +02:00
mwojcik	0ce86317c9	zc706: added rough master/satellite drtio support	2021-07-29 15:38:23 +02:00
mwojcik	248530faf1	gateware: kasli_soc - first attempt at drtio	2021-07-29 13:41:02 +02:00
mwojcik	c0e2e11968	drtio_routing: changed warning message	2021-07-28 10:05:50 +02:00
mwojcik	97d95c37f5	satman: removed references to spi for now	2021-07-27 14:44:43 +02:00
mwojcik	4540b8ec98	share identifier_read between runtime and satman	2021-07-27 14:42:29 +02:00
mwojcik	4e5f1a0673	fixed compilation errors - runtime compiles now	2021-07-27 12:40:55 +02:00
mwojcik	76b085333f	annotation fixes - no_std in libboard_artiq	2021-07-27 11:00:53 +02:00
mwojcik	630a934df0	removed mentions of fail, updated alloc	2021-07-27 10:27:43 +02:00
mwojcik	0d7d403edc	merged proto_core_io with libio	2021-07-27 09:38:38 +02:00
mwojcik	5e39cd32d1	removed unused imports, added necessary.	2021-07-26 14:41:00 +02:00
mwojcik	522bea7e1c	reverted build script with linker file arg. Hybrid solution.	2021-07-26 14:38:43 +02:00
mwojcik	2c3091e792	experimental: build script with linker file arg	2021-07-26 13:57:37 +02:00
mwojcik	8b780ec83b	fixing compilation errors: moved libboard_zynq sources to src folder	2021-07-26 11:41:50 +02:00
mwojcik	e081ea926b	build script taken from runtime to libbuild_zynq, dependencies adjusted	2021-07-26 10:28:44 +02:00
mwojcik	a06b485b67	build files copied from build_misoc	2021-07-23 14:59:29 +02:00
mwojcik	3af0ee6242	satman: moved i2c to libboard_zynq (no wrapper)	2021-07-23 14:45:48 +02:00
mwojcik	b963bbbf77	satman: replaced ident with the one from runtime	2021-07-23 14:14:07 +02:00
mwojcik	415a3be8ce	satman: removed irq::exception ref - no direct replacement	2021-07-23 14:11:05 +02:00
mwojcik	0502737481	satman: replaced clock with GlobalTimer completely	2021-07-23 13:15:07 +02:00
mwojcik	5e76f7c0b4	moved proto, moved logger, updated runtime	2021-07-23 11:28:16 +02:00
mwojcik	f170104304	libboard_artiqzynq -> libboard_artiq; moved si5324	2021-07-23 11:15:31 +02:00
mwojcik	d309409a84	satman: removed jcdg completely	2021-07-23 11:00:48 +02:00
mwojcik	7b25bc710e	removed references for clock, replaced with timer	2021-07-22 14:39:27 +02:00
mwojcik	5fa575ce4c	drtio_routing: made to use libconfig; moved logger	2021-07-22 12:15:20 +02:00
mwojcik	2647ef7249	moved si5324, added notes on required porting	2021-07-22 12:15:18 +02:00
mwojcik	60a8861a22	added libboard_artiqzync (?), moved more libs	2021-07-22 12:15:12 +02:00
mwojcik	731f52992f	moved related libraries, culled unnecessary ones	2021-07-22 12:15:07 +02:00
mwojcik	7e97e86446	removed ad9154 and jesd204 stuff; notes on ports	2021-07-22 12:14:58 +02:00
spaqin	3656fcc510	drtio: moved satman fw	2021-07-21 09:25:37 +02:00